From b251a7a37404e68fb632a384a7bb4faacf1858b0 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 19 Oct 2020 14:08:17 +0530 Subject: [PATCH] ARM: dts: msm: Add UFS support for direwolf Add UFS host controller and UFS PHY (attached to embedded UFS card) for direwolf platform. Change-Id: I0f2858f6bef5a275d362cec3909a13a70cdfd14b --- qcom/direwolf-adp-common.dtsi | 28 +++++++ qcom/direwolf.dtsi | 137 +++++++++++++++++++++++++++++++++- 2 files changed, 164 insertions(+), 1 deletion(-) diff --git a/qcom/direwolf-adp-common.dtsi b/qcom/direwolf-adp-common.dtsi index 23df450781cf..393f11c54700 100644 --- a/qcom/direwolf-adp-common.dtsi +++ b/qcom/direwolf-adp-common.dtsi @@ -1,3 +1,31 @@ &soc { }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4-lahaina"; + + vdda-phy-supply = <&L8G0>; + vdda-pll-supply = <&L3G0>; + vdda-phy-max-microamp = <85700>; + vdda-pll-max-microamp = <18300>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L17C0>; + vcc-voltage-level = <2504000 2504000>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L6C0>; + vccq-max-microamp = <750000>; + + qcom,vddp-ref-clk-supply = <&L6C0>; + qcom,vddp-ref-clk-max-microamp = <100>; + + status = "ok"; +}; diff --git a/qcom/direwolf.dtsi b/qcom/direwolf.dtsi index 0d5e78727299..98ff935a1075 100644 --- a/qcom/direwolf.dtsi +++ b/qcom/direwolf.dtsi @@ -28,7 +28,9 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; - aliases { }; + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ + }; cpus { #address-cells = <2>; @@ -906,6 +908,139 @@ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe10>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_REF_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d88000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <1492582 0>, <102400 0>, /* HS G3 RA */ + <2915200 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <1492582 0>, <204800 0>, /* HS G3 RA L2 */ + <2915200 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <1492582 0>, <102400 0>, /* HS G3 RB */ + <2915200 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */ + <2915200 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + iommus = <&apps_smmu 0xE0 0x0>; + qcom,iommu-dma = "fastmap"; + dma-coherent; + + rpm-level = <3>; + spm-level = <5>; + + status = "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0x1100>,