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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
qcacld-3.0: Add host support to configure the SMPS parameters
Currently there is no support to configure SMPS parameter from host, add support to configure SMPS parameters using ini. Change-Id: I6f8273ffed39a0b95c31f1647e86406b870165f2 CRs-Fixed: 2080571
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8 changed files with 187 additions and 0 deletions
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@ -11023,6 +11023,75 @@ enum hdd_external_acs_freq_band {
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#define CFG_LPRx_MAX (1)
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#define CFG_LPRx_DEFAULT (1)
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/*
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* <ini>
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* gUpperBrssiThresh - Sets Upper threshold for beacon RSSI
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* @Min: 36
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* @Max: 66
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* @Default: 46
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*
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* This ini sets Upper beacon threshold for beacon RSSI in FW
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* Used to reduced RX chainmask in FW, once this threshold is
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* reached FW will switch to 1X1 (Single chain).
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*
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* Supported Feature: STA
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_UPPER_BRSSI_THRESH_NAME "gUpperBrssiThresh"
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#define CFG_UPPER_BRSSI_THRESH_MIN (36)
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#define CFG_UPPER_BRSSI_THRESH_MAX (66)
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#define CFG_UPPER_BRSSI_THRESH_DEFAULT (46)
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/*
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* <ini>
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* gLowerrBrssiThresh - Sets Lower threshold for beacon RSSI
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* @Min: 6
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* @Max: 36
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* @Default: 26
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*
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* This ini sets Lower beacon threshold for beacon RSSI in FW
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* Used to increase RX chainmask in FW, once this threshold is
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* reached FW will switch to 2X2 chain.
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*
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* Supported Feature: STA
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_LOWER_BRSSI_THRESH_NAME "gLowerBrssiThresh"
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#define CFG_LOWER_BRSSI_THRESH_MIN (6)
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#define CFG_LOWER_BRSSI_THRESH_MAX (36)
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#define CFG_LOWER_BRSSI_THRESH_DEFAULT (26)
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/*
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* <ini>
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* gDtim1ChRxEnable - Enable/Disable DTIM 1Chrx feature
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* @Min: 0
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* @Max: 1
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* @Default: 1
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*
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* This ini Enables or Disables DTIM 1CHRX feature in FW
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* If this flag is set FW enables shutting off one chain
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* while going to power save.
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*
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* Supported Feature: STA
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*
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* Usage: External
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*
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* </ini>
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*/
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#define CFG_DTIM_1CHRX_ENABLE_NAME "gDtim1ChRxEnable"
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#define CFG_DTIM_1CHRX_ENABLE_MIN (0)
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#define CFG_DTIM_1CHRX_ENABLE_MAX (1)
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#define CFG_DTIM_1CHRX_ENABLE_DEFAULT (1)
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/*
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* Type declarations
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*/
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@ -11786,6 +11855,9 @@ struct hdd_config {
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uint8_t rssi_penalize_factor_5g;
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uint8_t max_rssi_penalize_5g;
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bool enable_lprx;
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uint8_t upper_brssi_thresh;
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uint8_t lower_brssi_thresh;
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bool enable_dtim_1chrx;
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};
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#define VAR_OFFSET(_Struct, _Var) (offsetof(_Struct, _Var))
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@ -1351,6 +1351,29 @@ struct suspend_resume_stats {
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uint32_t suspend_fail[SUSPEND_FAIL_MAX_COUNT];
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};
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/**
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* hdd_sta_smps_param - SMPS parameters to configure from hdd
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* HDD_STA_SMPS_PARAM_UPPER_RSSI_THRESH: RSSI threshold to enter Dynamic SMPS
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* mode from inactive mode
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* HDD_STA_SMPS_PARAM_STALL_RSSI_THRESH: RSSI threshold to enter
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* Stalled-D-SMPS mode from D-SMPS mode or to enter D-SMPS mode from
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* Stalled-D-SMPS mode
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* HDD_STA_SMPS_PARAM_LOWER_RSSI_THRESH: RSSI threshold to disable SMPS modes
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* HDD_STA_SMPS_PARAM_UPPER_BRSSI_THRESH: Upper threshold for beacon-RSSI.
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* Used to reduce RX chainmask.
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* HDD_STA_SMPS_PARAM_LOWER_BRSSI_THRESH: Lower threshold for beacon-RSSI.
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* Used to increase RX chainmask.
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* HDD_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE: Enable/Disable DTIM 1chRx feature
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*/
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enum hdd_sta_smps_param {
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HDD_STA_SMPS_PARAM_UPPER_RSSI_THRESH = 0,
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HDD_STA_SMPS_PARAM_STALL_RSSI_THRESH = 1,
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HDD_STA_SMPS_PARAM_LOWER_RSSI_THRESH = 2,
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HDD_STA_SMPS_PARAM_UPPER_BRSSI_THRESH = 3,
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HDD_STA_SMPS_PARAM_LOWER_BRSSI_THRESH = 4,
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HDD_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5
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};
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/** Adapter structure definition */
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struct hdd_context_s {
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/** Global CDS context */
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@ -4590,6 +4590,27 @@ struct reg_table_entry g_registry_table[] = {
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CFG_LPRx_DEFAULT,
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CFG_LPRx_MIN,
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CFG_LPRx_MAX),
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REG_VARIABLE(CFG_UPPER_BRSSI_THRESH_NAME, WLAN_PARAM_Integer,
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struct hdd_config, upper_brssi_thresh,
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VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
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CFG_UPPER_BRSSI_THRESH_DEFAULT,
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CFG_UPPER_BRSSI_THRESH_MIN,
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CFG_UPPER_BRSSI_THRESH_MAX),
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REG_VARIABLE(CFG_LOWER_BRSSI_THRESH_NAME, WLAN_PARAM_Integer,
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struct hdd_config, lower_brssi_thresh,
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VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
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CFG_LOWER_BRSSI_THRESH_DEFAULT,
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CFG_LOWER_BRSSI_THRESH_MIN,
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CFG_LOWER_BRSSI_THRESH_MAX),
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REG_VARIABLE(CFG_DTIM_1CHRX_ENABLE_NAME, WLAN_PARAM_Integer,
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struct hdd_config, enable_dtim_1chrx,
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VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
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CFG_DTIM_1CHRX_ENABLE_DEFAULT,
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CFG_DTIM_1CHRX_ENABLE_MIN,
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CFG_DTIM_1CHRX_ENABLE_MAX),
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};
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@ -6145,6 +6166,15 @@ void hdd_cfg_print(hdd_context_t *pHddCtx)
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hdd_debug("Name = [%s] value = [%u]",
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CFG_LPRx_NAME,
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pHddCtx->config->enable_lprx);
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hdd_debug("Name = [%s] value = [%u]",
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CFG_UPPER_BRSSI_THRESH_NAME,
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pHddCtx->config->upper_brssi_thresh);
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hdd_debug("Name = [%s] value = [%u]",
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CFG_LOWER_BRSSI_THRESH_NAME,
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pHddCtx->config->lower_brssi_thresh);
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hdd_debug("Name = [%s] value = [%u]",
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CFG_DTIM_1CHRX_ENABLE_NAME,
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pHddCtx->config->enable_dtim_1chrx);
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}
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@ -3641,6 +3641,20 @@ int hdd_set_fw_params(hdd_adapter_t *adapter)
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goto error;
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}
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if (adapter->device_mode == QDF_STA_MODE) {
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sme_set_smps_cfg(adapter->sessionId,
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HDD_STA_SMPS_PARAM_UPPER_BRSSI_THRESH,
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hdd_ctx->config->upper_brssi_thresh);
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sme_set_smps_cfg(adapter->sessionId,
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HDD_STA_SMPS_PARAM_LOWER_BRSSI_THRESH,
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hdd_ctx->config->lower_brssi_thresh);
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sme_set_smps_cfg(adapter->sessionId,
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HDD_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE,
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hdd_ctx->config->enable_dtim_1chrx);
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}
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if (hdd_ctx->config->enable2x2) {
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hdd_debug("configuring 2x2 mode fw params");
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@ -1650,6 +1650,17 @@ int sme_cli_set_command(int vdev_id, int param_id, int sval, int vpdev);
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QDF_STATUS sme_set_bt_activity_info_cb(tHalHandle hal,
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void (*cb)(void *, uint32_t profile_info));
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/**
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* sme_set_smps_cfg() - set SMPS config params
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* @vdev_id: virtual device for the command
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* @param_id: parameter id
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* @param_val: parameter value
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*
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* Return: QDF_STATUS_SUCCESS or non-zero on failure
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*/
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QDF_STATUS sme_set_smps_cfg(uint32_t vdev_id, uint32_t param_id,
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uint32_t param_val);
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/**
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* sme_get_peer_info() - sme api to get peer info
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* @hal: hal handle for getting global mac struct
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@ -16505,6 +16505,12 @@ QDF_STATUS sme_congestion_register_callback(tHalHandle hal,
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return status;
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}
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QDF_STATUS sme_set_smps_cfg(uint32_t vdev_id, uint32_t param_id,
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uint32_t param_val)
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{
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return wma_configure_smps_params(vdev_id, param_id, param_val);
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}
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QDF_STATUS sme_ipa_uc_stat_request(tHalHandle hal, uint32_t vdev_id,
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uint32_t param_id, uint32_t param_val, uint32_t req_cat)
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{
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@ -2560,6 +2560,15 @@ QDF_STATUS wma_set_rx_reorder_timeout_val(tp_wma_handle wma_handle,
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*/
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QDF_STATUS wma_set_rx_blocksize(tp_wma_handle wma_handle,
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struct sir_peer_set_rx_blocksize *peer_rx_blocksize);
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/**
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* wma_configure_smps_params() - Configures the smps parameters to set
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* @vdev_id: Virtual device for the command
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* @param_id: SMPS parameter ID
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* @param_val: Value to be set for the parameter
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* Return: QDF_STATUS_SUCCESS or non-zero on failure
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*/
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QDF_STATUS wma_configure_smps_params(uint32_t vdev_id, uint32_t param_id,
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uint32_t param_val);
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/*
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* wma_chip_power_save_failure_detected_handler() - chip pwr save fail detected
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@ -7699,6 +7699,28 @@ int wma_peer_rx_reorder_queue_remove(void *scn_handle,
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¶m);
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}
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QDF_STATUS wma_configure_smps_params(uint32_t vdev_id, uint32_t param_id,
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uint32_t param_val)
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{
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tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA);
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int smps_cmd_value;
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int status = QDF_STATUS_E_INVAL;
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if (!wma) {
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WMA_LOGE("%s: Failed to get wma", __func__);
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return status;
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}
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smps_cmd_value = param_id << WMI_SMPS_PARAM_VALUE_S;
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smps_cmd_value = smps_cmd_value | param_val;
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status = wma_set_smps_params(wma, vdev_id, smps_cmd_value);
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if (status)
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WMA_LOGE("Failed to set SMPS Param");
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return status;
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}
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void wma_ipa_uc_stat_request(wma_cli_set_cmd_t *privcmd)
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{
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