From 4dfb4bb8ae1eb25ddba53afaa1c9bda843adf181 Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Mon, 6 Apr 2020 13:28:34 -0700
Subject: [PATCH 1/2] ARM: dts: msm: Update PCIe0 PHY settings to v0.97.1 for
 lahaina

Update PCIe0 PHY setting to version 0.97.1 based on hardware
recommendation for lahaina. Also enables SSC.

Change-Id: I9205b7aed9c9603f689335300a225b367f120bfe
---
 qcom/lahaina-pcie.dtsi | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 088dad1816b6..85c0eac3b849 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -109,7 +109,7 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 
-		qcom,pcie-phy-ver = <10921>;
+		qcom,pcie-phy-ver = <10971>;
 		qcom,phy-status-offset = <0x214>;
 		qcom,phy-status-bit = <6>;
 		qcom,phy-power-down-offset = <0x240>;
@@ -144,26 +144,49 @@
 				0x0080 0x16 0x0
 				0x0088 0x36 0x0
 				0x01b0 0x1e 0x0
-				0x01ac 0xb9 0x0
+				0x01ac 0xca 0x0
 				0x01b8 0x18 0x0
-				0x01b4 0x94 0x0
+				0x01b4 0xa2 0x0
 				0x0050 0x07 0x0
-				0x0010 0x00 0x0
+				0x0010 0x01 0x0
 				0x001c 0x31 0x0
 				0x0020 0x01 0x0
 				0x0024 0xde 0x0
 				0x0028 0x07 0x0
 				0x0030 0x4c 0x0
 				0x0034 0x06 0x0
+				0x0ee4 0x20 0x0
+				0x0e84 0x75 0x0
+				0x0e90 0x3f 0x0
+				0x115c 0x7f 0x0
+				0x1160 0xff 0x0
+				0x1164 0xbf 0x0
+				0x1168 0x3f 0x0
+				0x116c 0xd8 0x0
+				0x1170 0xdc 0x0
+				0x1174 0xdc 0x0
+				0x1178 0x5c 0x0
+				0x117c 0x34 0x0
+				0x1180 0xa6 0x0
+				0x1190 0x34 0x0
+				0x10d8 0x07 0x0
+				0x0e40 0x0c 0x0
+				0x10dc 0x00 0x0
+				0x104c 0x08 0x0
+				0x1050 0x08 0x0
+				0x1044 0xf0 0x0
+				0x11a4 0x38 0x0
 				0x0694 0x00 0x0
 				0x0654 0x00 0x0
 				0x06a8 0x0f 0x0
-				0x0048 0x90 0x0
+				0x0044 0x04 0x0
+				0x0048 0xb0 0x0
 				0x0620 0xc1 0x0
 				0x0388 0xa8 0x0
-				0x0398 0x0b 0x0
-				0x02dc 0x0d 0x0
 				0x10b0 0x18 0x0
+				0x0608 0x0f 0x0
+				0x0398 0x0b 0x0
+				0x02dc 0x05 0x0
 				0x0200 0x00 0x0
 				0x0244 0x03 0x0>;
 

From 4ce97d3889f73e20010ff96423c137bf9cba6bbd Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Tue, 28 Apr 2020 17:05:44 -0700
Subject: [PATCH 2/2] ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL
 on lahaina

PCIe0 needs to manage PHY PLL on lahaina. Therefore add the DT
entries so that PCIe0 has to correct information to support this
request.

Change-Id: I622b4d3dc24e530554c23cbeeb0ee6dd528e5587
---
 qcom/lahaina-pcie.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 85c0eac3b849..ecabac665563 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -109,6 +109,11 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 
+		qcom,phy-manage-pll = <1>;
+		qcom,phy-resetsm-cntrl2 = <0xa0>;
+		qcom,phy-core-pll-en-mux = <7>;
+		qcom,phy-c-ready-status = <0x178>;
+
 		qcom,pcie-phy-ver = <10971>;
 		qcom,phy-status-offset = <0x214>;
 		qcom,phy-status-bit = <6>;