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cnss2: Make sure PCIe link is in L0 state before updating time sync

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Current driver will check PCIe link status by reading PCIe config space
before updating time sync registers. However, there is a drawback to use
PCIe API pci_read_config_word() to access config space since it will
disable interrupt and then perform read. If PCIe link is in L1 or L1ss
state, there may be more than 4ms needed to change the link state to L0
in order to access so it will cause jank for other time critical tasks.
Hence make sure PCIe link is in L0 state before updating time sync
registers instead of checking config space.

Change-Id: I59ca63c38b5af9e38e5a04d8e679f4dfde294746
Signed-off-by: Yue Ma <yuem@codeaurora.org>
This commit is contained in:
Yue Ma 2020-03-23 15:07:46 -07:00 • committed by Gerrit - the friendly Code Review server
commit b29497153c
1 changed files with 7 additions and 4 deletions
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11
drivers/net/wireless/cnss2/pci.c
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@ -1265,18 +1265,19 @@ static void cnss_pci_clear_time_sync_counter(struct cnss_pci_data *pci_priv)
static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv)
{
struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
struct device *dev = &pci_priv->pci_dev->dev;
unsigned long flags = 0;
u64 host_time_us, device_time_us, offset;
u32 low, high;
int ret;
ret = cnss_pci_check_link_status(pci_priv);
ret = cnss_pci_prevent_l1(dev);
if (ret)
return ret;
goto out;
ret = cnss_pci_force_wake_get(pci_priv);
if (ret)
return ret;
goto allow_l1;
spin_lock_irqsave(&time_sync_lock, flags);
cnss_pci_clear_time_sync_counter(pci_priv);
@ -1313,7 +1314,9 @@ static int cnss_pci_update_timestamp(struct cnss_pci_data *pci_priv)
force_wake_put:
cnss_pci_force_wake_put(pci_priv);
allow_l1:
cnss_pci_allow_l1(dev);
out:
return ret;
}