From b2bc33ab7f76028b2f57fcd344f4b843521b6258 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 24 Mar 2026 18:02:12 -0700 Subject: [PATCH] fw-api: CL 32023116 - update fw common interface files Change-Id: I41fd396e1c21471630e06770d2183b237cdc91ae CRs-Fixed: 3830439 --- fw/htt.h | 167 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 166 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 030a62cf081d..b6411c191bd6 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -282,9 +282,10 @@ * 3.152 Add decap_type in htt_rx_peer_metadata_v1b. * 3.153 Add passthru_pkt flag in rx_peer_metadata structs. * 3.154 Add T2H PEER_DEL_ALL_GLOBAL_VDEV_ID_UNMAP msg def. + * 3.155 Add rxmon hdrlen specs in rx_ring_selection_cfg_t. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 154 +#define HTT_CURRENT_VERSION_MINOR 155 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -6197,6 +6198,11 @@ enum htt_srng_ring_id { * dword28- b'0-31 - packet_type_enable_data_fpmo_flags_1 - filter bmap for * full pkt buffer each mode ctrl/data type/subtype for * fpmo mode + * dword29- b'0-31 - rdi_based_source_cfg + * Each bit maps to an RDI; if set, the corresponding + * ring ID is configured as a source buffer. + * Applies only to HTT_RXDMA_WBM_BUF0/1/2_RING. + * dword30- b'0-31 - wifi8 header length configurations. */ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 msg_type: 8, @@ -6280,6 +6286,21 @@ PREPACK struct htt_rx_ring_selection_cfg_t { * Below Field only applies for HTT_RXDMA_WBM_BUF0/1/2_RING */ A_UINT32 rdi_based_source_cfg; + + A_UINT32 rxmon_fpmo_data_hdrlen : 2, + rxmon_fpmo_ctrl_hdrlen : 2, + rxmon_fpmo_mgmt_hdrlen : 2, + rxmon_fp_data_hdrlen : 2, + rxmon_fp_ctrl_hdrlen : 2, + rxmon_fp_mgmt_hdrlen : 2, + rxmon_mo_data_hdrlen : 2, + rxmon_mo_ctrl_hdrlen : 2, + rxmon_mo_mgmt_hdrlen : 2, + rxmon_md_data_hdrlen : 2, + rxmon_md_ctrl_hdrlen : 2, + rxmon_md_mgmt_hdrlen : 2, + rxmon_enable_hdr_per_ppdu : 1, + rxmon_rsvd : 7; } POSTPACK; /** @@ -6963,6 +6984,150 @@ enum htt_reg_write_selection { } while (0) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M 0x00000003 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S 0 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_DATA_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M 0x0000000C +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S 2 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_CTRL_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M 0x00000030 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S 4 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FPMO_MGMT_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M 0x000000C0 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S 6 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_DATA_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M 0x00000300 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S 8 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_CTRL_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M 0x00000C00 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S 10 +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_FP_MGMT_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M 0x00003000 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S 12 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_DATA_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M 0x0000C000 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S 14 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_CTRL_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M 0x00030000 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S 16 +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMON_MO_MGMT_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M 0x000C0000 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S 18 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_DATA_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M 0x00300000 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S 20 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_CTRL_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M 0x00C00000 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S 22 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S) +#define HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_MD_MGMT_HDRLEN_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M 0x01000000 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S 24 +#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_M) >> \ + HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S) +#define HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RXMDN_ENABLE_HEADER_PER_PPDU_S)); \ + } while (0) + + /* * Subtype based MGMT frames enable bits. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other