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msm: kgsl: Don't deassert GBIF halt for non-GMU targets

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During adreno_stop, GBIF halt is asserted to halt any new transaction from
GPU before GPU power collapse, but in current code it is cleared
immediately which can allow few GPU transactions to go through before gdsc
is turned-off and can result in issues.

To avoid this situation don't deassert this halt before GPU gdsc goes off.
It will deassert automatically when gdsc goes off but in case gdsc doesn't
toggle as it is a shared resource, it is deasserted during adreno_start to
ensure wake-up doesn't fail.

Change-Id: If0a892470d04a0f3a79a1ea882ee5bfd16ad24ed
Signed-off-by: Puranam V G Tejaswi <pvgtejas@codeaurora.org>
This commit is contained in:
Puranam V G Tejaswi 2020-11-19 00:18:49 +05:30
commit b2cdc0d790
2 changed files with 8 additions and 4 deletions
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10
drivers/gpu/msm/adreno_a6xx_gmu.c
View file

@ -1626,6 +1626,8 @@ static void a6xx_gmu_pwrctrl_suspend(struct adreno_device *adreno_dev)
}
/* Halt CX traffic */
a6xx_halt_gbif(adreno_dev);
/* De-assert the halts */
kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0);
}
if (a6xx_gmu_gx_is_on(device))
@ -2764,9 +2766,6 @@ int a6xx_halt_gbif(struct adreno_device *adreno_dev)
ret = adreno_wait_for_halt_ack(device,
A6XX_GBIF_HALT_ACK, A6XX_GBIF_ARB_HALT_MASK);
/* De-assert the halts */
kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0);
return ret;
}
@ -2797,8 +2796,11 @@ static int a6xx_gmu_power_off(struct adreno_device *adreno_dev)
a6xx_rdpm_mx_freq_update(gmu, 0);
/* Now that we are done with GMU and GPU, Clear the GBIF */
if (!adreno_is_a630(adreno_dev))
if (!adreno_is_a630(adreno_dev)) {
ret = a6xx_halt_gbif(adreno_dev);
/* De-assert the halts */
kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0);
}
a6xx_gmu_irq_disable(adreno_dev);

2
drivers/gpu/msm/adreno_a6xx_hwsched.c
View file

@ -373,6 +373,8 @@ static int a6xx_hwsched_gmu_power_off(struct adreno_device *adreno_dev)
/* Now that we are done with GMU and GPU, Clear the GBIF */
ret = a6xx_halt_gbif(adreno_dev);
/* De-assert the halts */
kgsl_regwrite(device, A6XX_GBIF_HALT, 0x0);
a6xx_gmu_irq_disable(adreno_dev);