A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-09 21:59:12 -04:00
Code Issues Projects Releases Packages Wiki Activity

Revert "cnss2: Add support for bus bandwidth scale"

Browse source 
This reverts commit c1284ad3b8.

Change-Id: Icc94b6d0b880260601218f7040baf4755e180b5f
Signed-off-by: Manikandan Mohan <manikand@codeaurora.org>
This commit is contained in:
Manikandan Mohan 2020-03-28 12:01:00 -07:00
commit b2f765d2d7
1 changed files with 0 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

24
drivers/net/wireless/cnss2/pci.c
View file

@ -1076,20 +1076,16 @@ static int cnss_pci_set_mhi_state(struct cnss_pci_data *pci_priv,
ret = 0;
break;
case CNSS_MHI_SUSPEND:
mutex_lock(&pci_priv->mhi_ctrl->pm_mutex);
if (pci_priv->drv_connected_last)
ret = mhi_pm_fast_suspend(pci_priv->mhi_ctrl, true);
else
ret = mhi_pm_suspend(pci_priv->mhi_ctrl);
mutex_unlock(&pci_priv->mhi_ctrl->pm_mutex);
break;
case CNSS_MHI_RESUME:
mutex_lock(&pci_priv->mhi_ctrl->pm_mutex);
if (pci_priv->drv_connected_last)
ret = mhi_pm_fast_resume(pci_priv->mhi_ctrl, true);
else
ret = mhi_pm_resume(pci_priv->mhi_ctrl);
mutex_unlock(&pci_priv->mhi_ctrl->pm_mutex);
break;
case CNSS_MHI_TRIGGER_RDDM:
ret = mhi_force_rddm_mode(pci_priv->mhi_ctrl);
@ -4085,25 +4081,6 @@ static int cnss_pci_update_fw_name(struct cnss_pci_data *pci_priv)
return 0;
}
static int cnss_mhi_bw_scale(struct mhi_controller *mhi_ctrl,
struct mhi_link_info *link_info)
{
struct cnss_pci_data *pci_priv = mhi_ctrl->priv_data;
int ret = 0;
ret = msm_pcie_set_link_bandwidth(pci_priv->pci_dev,
link_info->target_link_speed,
link_info->target_link_width);
if (ret)
return ret;
cnss_pr_dbg("Setting link speed:0x%x, width:0x%x\n",
link_info->target_link_speed,
link_info->target_link_width);
return 0;
}
static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv)
{
int ret = 0;
@ -4152,7 +4129,6 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv)
mhi_ctrl->status_cb = cnss_mhi_notify_status;
mhi_ctrl->runtime_get = cnss_mhi_pm_runtime_get;
mhi_ctrl->runtime_put = cnss_mhi_pm_runtime_put_noidle;
mhi_ctrl->bw_scale = cnss_mhi_bw_scale;
mhi_ctrl->rddm_size = pci_priv->plat_priv->ramdump_info_v2.ramdump_size;
mhi_ctrl->sbl_size = SZ_512K;