From b307571af91756f75a94bbb87f76e7d6707647df Mon Sep 17 00:00:00 2001 From: houdz1 Date: Tue, 4 Jan 2022 09:29:10 +0800 Subject: [PATCH] msm/dsi: phy_v3.0: get strength volue of phy from dtsi Some project need to change the strength volue of phy, to fix the RF issue.So we can define the strength at the panel dtsi file. Change-Id: I9b3fb6e741798ac6ef5ec3921875a9975ce88e9f Signed-off-by: houdz1 Reviewed-on: https://gerrit.mot.com/2160545 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Yeqing Wang Reviewed-by: Huosheng Liao Submit-Approved: Jira Key --- msm/dsi/dsi_phy_hw_v3_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/msm/dsi/dsi_phy_hw_v3_0.c b/msm/dsi/dsi_phy_hw_v3_0.c index 4b8992bc07c3..a73c89f537a5 100644 --- a/msm/dsi/dsi_phy_hw_v3_0.c +++ b/msm/dsi/dsi_phy_hw_v3_0.c @@ -185,6 +185,12 @@ static void dsi_phy_hw_v3_0_lane_settings(struct dsi_phy_hw *phy, DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(i), 0); DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i), 0x0); DSI_W32(phy, DSIPHY_LNX_HSTX_STR_CTRL(i), 0x88); + if(cfg->phy_drive_strength) { + DSI_W32(phy, DSIPHY_LNX_HSTX_STR_CTRL(i), cfg->phy_drive_strength); + DSI_PHY_WARN(phy, "DSIPHY_LNX_HSTX_STR_CTRL of lane%d is rewrite to 0x%x from 0x88\n", + i, cfg->phy_drive_strength); + } + } dsi_phy_hw_v3_0_config_lpcdrx(phy, cfg, true);