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usb: dwc3: Add tuning support for Gen2 Tx compliance parameters

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This change provides the infrastructure required to tune Gen2
Tx compliance parameters via device tree. The tuning values
provided through dt properties are written to the corresponding
de-emph dwc3 registers during core initialization.

Change-Id: I38015a6f12ca27247bce5ea805d86322122f3466
Signed-off-by: Elson Roy Serrao <eserrao@codeaurora.org>
This commit is contained in:
Elson Roy Serrao 2019-11-20 20:32:18 -08:00
commit b30d71c470
2 changed files with 40 additions and 0 deletions
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29
drivers/usb/dwc3/core.c
View file

@ -1088,6 +1088,19 @@ int dwc3_core_init(struct dwc3 *dwc)
}
}
if (dwc->gen2_tx_de_emph != -1)
dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH(0),
dwc->gen2_tx_de_emph & DWC31_TX_DEEMPH_MASK);
if (dwc->gen2_tx_de_emph1 != -1)
dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_1(0),
dwc->gen2_tx_de_emph1 & DWC31_TX_DEEMPH_MASK);
if (dwc->gen2_tx_de_emph2 != -1)
dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_2(0),
dwc->gen2_tx_de_emph2 & DWC31_TX_DEEMPH_MASK);
if (dwc->gen2_tx_de_emph3 != -1)
dwc3_writel(dwc->regs, DWC31_LCSR_TX_DEEMPH_3(0),
dwc->gen2_tx_de_emph3 & DWC31_TX_DEEMPH_MASK);
/* set inter-packet gap 199.794ns to improve EL_23 margin */
if (dwc->revision >= DWC3_USB31_REVISION_170A) {
reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
@ -1397,6 +1410,22 @@ static void dwc3_get_properties(struct dwc3 *dwc)
device_property_read_u32(dev, "snps,xhci-imod-value",
&dwc->xhci_imod_value);
dwc->gen2_tx_de_emph = -1;
device_property_read_u32(dev, "snps,gen2-tx-de-emph",
&dwc->gen2_tx_de_emph);
dwc->gen2_tx_de_emph1 = -1;
device_property_read_u32(dev, "snps,gen2-tx-de-emph1",
&dwc->gen2_tx_de_emph1);
dwc->gen2_tx_de_emph2 = -1;
device_property_read_u32(dev, "snps,gen2-tx-de-emph2",
&dwc->gen2_tx_de_emph2);
dwc->gen2_tx_de_emph3 = -1;
device_property_read_u32(dev, "snps,gen2-tx-de-emph3",
&dwc->gen2_tx_de_emph3);
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
dwc->tx_de_emphasis = tx_de_emphasis;

11
drivers/usb/dwc3/core.h
View file

@ -171,6 +171,13 @@
#define GEN1_U3_EXIT_RSP_RX_CLK_MASK GEN1_U3_EXIT_RSP_RX_CLK(0xff)
#define DWC31_LINK_GDBGLTSSM 0xd050
/* DWC 3.1 Tx De-emphasis Registers */
#define DWC31_LCSR_TX_DEEMPH(n) (0xd060 + ((n) * 0x80))
#define DWC31_LCSR_TX_DEEMPH_1(n) (0xd064 + ((n) * 0x80))
#define DWC31_LCSR_TX_DEEMPH_2(n) (0xd068 + ((n) * 0x80))
#define DWC31_LCSR_TX_DEEMPH_3(n) (0xd06c + ((n) * 0x80))
#define DWC31_TX_DEEMPH_MASK 0x3ffff
/* Bit fields */
/* Global SoC Bus Configuration Register 1 */
@ -1356,6 +1363,10 @@ struct dwc3 {
*/
bool host_poweroff_in_pm_suspend;
int retries_on_error;
u32 gen2_tx_de_emph;
u32 gen2_tx_de_emph1;
u32 gen2_tx_de_emph2;
u32 gen2_tx_de_emph3;
};
#define INCRX_BURST_MODE 0