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msm: pcie: correct PCIe target link speed mask macro

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When setting target link speed, it is correct to use
PCI_EXP_LNKCTL2_TLS instead of PCI_EXP_LNKCAP_SLS and
PCI_EXP_LNKSTA_CLS. All 3 macros have the same value defined
but it is proper to use the right one.

Change-Id: I5d99a696168170adf8dc577a6bf1fceb4fe82686
Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong 2020-10-21 17:51:35 -07:00
commit b3275a157a
1 changed files with 3 additions and 3 deletions
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6
drivers/pci/controller/pci-msm.c
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@ -3797,7 +3797,7 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev)
if (dev->target_link_speed)
msm_pcie_write_reg_field(dev->dm_core,
PCIE20_CAP + PCI_EXP_LNKCTL2,
PCI_EXP_LNKCAP_SLS, dev->target_link_speed);
PCI_EXP_LNKCTL2_TLS, dev->target_link_speed);
/* set max tlp read size */
msm_pcie_write_reg_field(dev->dm_core, PCIE20_DEVICE_CONTROL_STATUS,
@ -3861,7 +3861,7 @@ static int msm_pcie_link_train(struct msm_pcie_dev_t *dev)
if (bw_scale->cx_vreg_min < dev->cx_vreg->min_v) {
msm_pcie_write_reg_field(dev->dm_core,
PCIE20_CAP + PCI_EXP_LNKCTL2,
PCI_EXP_LNKCAP_SLS, current_link_speed);
PCI_EXP_LNKCTL2_TLS, current_link_speed);
msm_pcie_scale_link_bandwidth(dev, current_link_speed);
}
}
@ -6025,7 +6025,7 @@ int msm_pcie_set_link_bandwidth(struct pci_dev *pci_dev, u16 target_link_speed,
msm_pcie_config_clear_set_dword(root_pci_dev,
root_pci_dev->pcie_cap +
PCI_EXP_LNKCTL2,
PCI_EXP_LNKSTA_CLS,
PCI_EXP_LNKCTL2_TLS,
target_link_speed);
/* need to be in L0 for gen switch */