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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
* Samsung S5PV210 has been converted to DT and multiplatform
* Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
* Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood.
* Hwmod data for TI AM43xx and DRA7 platforms.
* More additions of Renesas shmobile platform support
* Removal of plat-samsung contents that can be removed with S5PV210 being
multiplatform/DT-enabled and the other two old platforms being removed.
New platforms (most with only basic support right now):
* Hisilicon X5HD2 settop box chipset is introduced
* Mediatek MT6589 (mobile chipset) is introduced
* Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code.
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Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This is the bulk of new SoC enablement and other platform changes for
3.17:
- Samsung S5PV210 has been converted to DT and multiplatform
- Clock drivers and bindings for some of the lower-end i.MX 1/2
platforms
- Kirkwood, one of the popular Marvell platforms, is folded into the
mvebu platform code, removing mach-kirkwood
- Hwmod data for TI AM43xx and DRA7 platforms
- More additions of Renesas shmobile platform support
- Removal of plat-samsung contents that can be removed with S5PV210
being multiplatform/DT-enabled and the other two old platforms
being removed
New platforms (most with only basic support right now):
- Hisilicon X5HD2 settop box chipset is introduced
- Mediatek MT6589 (mobile chipset) is introduced
- Broadcom BCM7xxx settop box chipset is introduced
+ as usual a lot other pieces all over the platform code"
* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
ARM: hisi: remove smp from machine descriptor
power: reset: move hisilicon reboot code
ARM: dts: Add hix5hd2-dkb dts file.
ARM: debug: Rename Hi3716 to HIX5HD2
ARM: hisi: enable hix5hd2 SoC
ARM: hisi: add ARCH_HISI
MAINTAINERS: add entry for Broadcom ARM STB architecture
ARM: brcmstb: select GISB arbiter and interrupt drivers
ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
ARM: configs: enable SMP in bcm_defconfig
ARM: add SMP support for Broadcom mobile SoCs
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
...
This commit is contained in:
Linus Torvalds
commit
b3345d7c57
407 changed files with 11489 additions and 19492 deletions
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@ -1166,234 +1166,9 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
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#endif
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};
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/*
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* Followings are the gpio banks in S5PV210/S5PC110
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*
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* The 'config' member when left to NULL, is initialized to the default
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* structure samsung_gpio_cfgs[3] in the init function below.
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*
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* The 'base' member is also initialized in the init function below.
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* Note: The initialization of 'base' member of samsung_gpio_chip structure
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* uses the above macro and depends on the banks being listed in order here.
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*/
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static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
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#ifdef CONFIG_CPU_S5PV210
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{
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.chip = {
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.base = S5PV210_GPA0(0),
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.ngpio = S5PV210_GPIO_A0_NR,
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.label = "GPA0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPA1(0),
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.ngpio = S5PV210_GPIO_A1_NR,
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.label = "GPA1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPB(0),
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.ngpio = S5PV210_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC0(0),
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.ngpio = S5PV210_GPIO_C0_NR,
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.label = "GPC0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPC1(0),
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.ngpio = S5PV210_GPIO_C1_NR,
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.label = "GPC1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD0(0),
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.ngpio = S5PV210_GPIO_D0_NR,
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.label = "GPD0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPD1(0),
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.ngpio = S5PV210_GPIO_D1_NR,
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.label = "GPD1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE0(0),
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.ngpio = S5PV210_GPIO_E0_NR,
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.label = "GPE0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPE1(0),
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.ngpio = S5PV210_GPIO_E1_NR,
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.label = "GPE1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF0(0),
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.ngpio = S5PV210_GPIO_F0_NR,
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.label = "GPF0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF1(0),
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.ngpio = S5PV210_GPIO_F1_NR,
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.label = "GPF1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF2(0),
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.ngpio = S5PV210_GPIO_F2_NR,
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.label = "GPF2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPF3(0),
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.ngpio = S5PV210_GPIO_F3_NR,
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.label = "GPF3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG0(0),
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.ngpio = S5PV210_GPIO_G0_NR,
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.label = "GPG0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG1(0),
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.ngpio = S5PV210_GPIO_G1_NR,
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.label = "GPG1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG2(0),
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.ngpio = S5PV210_GPIO_G2_NR,
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.label = "GPG2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPG3(0),
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.ngpio = S5PV210_GPIO_G3_NR,
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.label = "GPG3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPI(0),
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.ngpio = S5PV210_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ0(0),
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.ngpio = S5PV210_GPIO_J0_NR,
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.label = "GPJ0",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ1(0),
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.ngpio = S5PV210_GPIO_J1_NR,
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.label = "GPJ1",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ2(0),
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.ngpio = S5PV210_GPIO_J2_NR,
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.label = "GPJ2",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ3(0),
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.ngpio = S5PV210_GPIO_J3_NR,
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.label = "GPJ3",
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},
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}, {
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.chip = {
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.base = S5PV210_GPJ4(0),
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.ngpio = S5PV210_GPIO_J4_NR,
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.label = "GPJ4",
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},
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}, {
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.chip = {
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.base = S5PV210_MP01(0),
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.ngpio = S5PV210_GPIO_MP01_NR,
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.label = "MP01",
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},
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}, {
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.chip = {
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.base = S5PV210_MP02(0),
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.ngpio = S5PV210_GPIO_MP02_NR,
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.label = "MP02",
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},
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}, {
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.chip = {
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.base = S5PV210_MP03(0),
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.ngpio = S5PV210_GPIO_MP03_NR,
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.label = "MP03",
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},
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}, {
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.chip = {
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.base = S5PV210_MP04(0),
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.ngpio = S5PV210_GPIO_MP04_NR,
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.label = "MP04",
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},
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}, {
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.chip = {
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.base = S5PV210_MP05(0),
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.ngpio = S5PV210_GPIO_MP05_NR,
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.label = "MP05",
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC00),
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.irq_base = IRQ_EINT(0),
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.chip = {
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.base = S5PV210_GPH0(0),
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.ngpio = S5PV210_GPIO_H0_NR,
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.label = "GPH0",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC20),
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.irq_base = IRQ_EINT(8),
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.chip = {
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.base = S5PV210_GPH1(0),
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.ngpio = S5PV210_GPIO_H1_NR,
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.label = "GPH1",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC40),
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.irq_base = IRQ_EINT(16),
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.chip = {
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.base = S5PV210_GPH2(0),
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.ngpio = S5PV210_GPIO_H2_NR,
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.label = "GPH2",
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.to_irq = samsung_gpiolib_to_irq,
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},
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}, {
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.base = (S5P_VA_GPIO + 0xC60),
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.irq_base = IRQ_EINT(24),
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.chip = {
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.base = S5PV210_GPH3(0),
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.ngpio = S5PV210_GPIO_H3_NR,
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.label = "GPH3",
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.to_irq = samsung_gpiolib_to_irq,
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},
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},
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#endif
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};
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/* TODO: cleanup soc_is_* */
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static __init int samsung_gpiolib_init(void)
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{
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struct samsung_gpio_chip *chip;
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int i, nr_chips;
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int group = 0;
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/*
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* Currently there are two drivers that can provide GPIO support for
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* Samsung SoCs. For device tree enabled platforms, the new
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@ -1417,21 +1192,6 @@ static __init int samsung_gpiolib_init(void)
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S3C64XX_VA_GPIO);
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samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
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ARRAY_SIZE(s3c64xx_gpios_4bit2));
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} else if (soc_is_s5pv210()) {
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group = 0;
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chip = s5pv210_gpios_4bit;
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nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
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for (i = 0; i < nr_chips; i++, chip++) {
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if (!chip->config) {
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chip->config = &samsung_gpio_cfgs[3];
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chip->group = group++;
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}
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}
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samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
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#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
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s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
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#endif
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} else {
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WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
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return -ENODEV;
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