From a59433a484c013922796da92653190b8cb57fac5 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Tue, 25 Aug 2020 17:14:49 +0800 Subject: [PATCH] soc: swr-mstr: update component and interrupt enable sequence Enable component after enabling interrupt to avoid missing some intterupt during master init. Change-Id: I0f60c5431a815c58f878d3b9275a046e47939111 Signed-off-by: Meng Wang --- soc/swr-mstr-ctrl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 6c85d817acf3..8ec255e80827 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -2482,9 +2482,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_COMP_CFG; value[len++] = 0x02; - reg[len] = SWRM_COMP_CFG; - value[len++] = 0x03; - reg[len] = SWRM_INTERRUPT_CLEAR; value[len++] = 0xFFFFFFFF; @@ -2496,6 +2493,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_CPU1_INTERRUPT_EN; value[len++] = swrm->intr_mask; + reg[len] = SWRM_COMP_CFG; + value[len++] = 0x03; + swr_master_bulk_write(swrm, reg, value, len); if (!swrm_check_link_status(swrm, 0x1)) {