mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next into for-davem
Conflicts: drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c drivers/staging/ath6kl/os/linux/ar6000_drv.c
This commit is contained in:
John W. Linville
commit
b38d355eaa
321 changed files with 22561 additions and 54152 deletions
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@ -6,6 +6,7 @@
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#include <linux/bcma/bcma_driver_chipcommon.h>
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#include <linux/bcma/bcma_driver_pci.h>
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#include <linux/bcma/bcma_driver_mips.h>
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#include <linux/ssb/ssb.h> /* SPROM sharing */
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#include "bcma_regs.h"
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@ -14,9 +15,9 @@ struct bcma_device;
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struct bcma_bus;
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enum bcma_hosttype {
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BCMA_HOSTTYPE_NONE,
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BCMA_HOSTTYPE_PCI,
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BCMA_HOSTTYPE_SDIO,
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BCMA_HOSTTYPE_SOC,
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};
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struct bcma_chipinfo {
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@ -130,6 +131,7 @@ struct bcma_device {
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struct device dev;
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struct device *dma_dev;
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unsigned int irq;
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bool dev_registered;
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@ -138,6 +140,9 @@ struct bcma_device {
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u32 addr;
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u32 wrap;
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void __iomem *io_addr;
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void __iomem *io_wrap;
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void *drvdata;
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struct list_head list;
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};
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@ -190,9 +195,11 @@ struct bcma_bus {
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struct bcma_device *mapped_core;
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struct list_head cores;
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u8 nr_cores;
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u8 init_done:1;
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struct bcma_drv_cc drv_cc;
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struct bcma_drv_pci drv_pci;
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struct bcma_drv_mips drv_mips;
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/* We decided to share SPROM struct with SSB as long as we do not need
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* any hacks for BCMA. This simplifies drivers code. */
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@ -24,6 +24,7 @@
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#define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
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#define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
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#define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
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#define BCMA_CC_FLASHT_NFLASH 0x00000200
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#define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
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#define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
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#define BCMA_PLLTYPE_NONE 0x00000000
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@ -178,6 +179,7 @@
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#define BCMA_CC_PROG_CFG 0x0120
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#define BCMA_CC_PROG_WAITCNT 0x0124
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#define BCMA_CC_FLASH_CFG 0x0128
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#define BCMA_CC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
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#define BCMA_CC_FLASH_WAITCNT 0x012C
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/* 0x1E0 is defined as shared BCMA_CLKCTLST */
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#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
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@ -239,6 +241,48 @@
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#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
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#define BCMA_CC_SPROM_PCIE6 0x0830 /* SPROM beginning on PCIe rev >= 6 */
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/* Divider allocation in 4716/47162/5356 */
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#define BCMA_CC_PMU5_MAINPLL_CPU 1
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#define BCMA_CC_PMU5_MAINPLL_MEM 2
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#define BCMA_CC_PMU5_MAINPLL_SSB 3
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/* PLL usage in 4716/47162 */
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#define BCMA_CC_PMU4716_MAINPLL_PLL0 12
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/* PLL usage in 5356/5357 */
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#define BCMA_CC_PMU5356_MAINPLL_PLL0 0
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#define BCMA_CC_PMU5357_MAINPLL_PLL0 0
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/* 4706 PMU */
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#define BCMA_CC_PMU4706_MAINPLL_PLL0 0
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/* ALP clock on pre-PMU chips */
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#define BCMA_CC_PMU_ALP_CLOCK 20000000
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/* HT clock for systems with PMU-enabled chipcommon */
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#define BCMA_CC_PMU_HT_CLOCK 80000000
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/* PMU rev 5 (& 6) */
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#define BCMA_CC_PPL_P1P2_OFF 0
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#define BCMA_CC_PPL_P1_MASK 0x0f000000
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#define BCMA_CC_PPL_P1_SHIFT 24
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#define BCMA_CC_PPL_P2_MASK 0x00f00000
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#define BCMA_CC_PPL_P2_SHIFT 20
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#define BCMA_CC_PPL_M14_OFF 1
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#define BCMA_CC_PPL_MDIV_MASK 0x000000ff
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#define BCMA_CC_PPL_MDIV_WIDTH 8
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#define BCMA_CC_PPL_NM5_OFF 2
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#define BCMA_CC_PPL_NDIV_MASK 0xfff00000
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#define BCMA_CC_PPL_NDIV_SHIFT 20
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#define BCMA_CC_PPL_FMAB_OFF 3
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#define BCMA_CC_PPL_MRAT_MASK 0xf0000000
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#define BCMA_CC_PPL_MRAT_SHIFT 28
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#define BCMA_CC_PPL_ABRAT_MASK 0x08000000
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#define BCMA_CC_PPL_ABRAT_SHIFT 27
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#define BCMA_CC_PPL_FDIV_MASK 0x07ffffff
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#define BCMA_CC_PPL_PLLCTL_OFF 4
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#define BCMA_CC_PPL_PCHI_OFF 5
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#define BCMA_CC_PPL_PCHI_MASK 0x0000003f
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/* Data for the PMU, if available.
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* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
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*/
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@ -247,14 +291,37 @@ struct bcma_chipcommon_pmu {
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u32 crystalfreq; /* The active crystal frequency (in kHz) */
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};
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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struct bcma_pflash {
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u8 buswidth;
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u32 window;
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u32 window_size;
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};
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struct bcma_serial_port {
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void *regs;
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unsigned long clockspeed;
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unsigned int irq;
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unsigned int baud_base;
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unsigned int reg_shift;
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};
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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struct bcma_drv_cc {
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struct bcma_device *core;
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u32 status;
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u32 capabilities;
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u32 capabilities_ext;
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u8 setup_done:1;
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/* Fast Powerup Delay constant */
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u16 fast_pwrup_delay;
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struct bcma_chipcommon_pmu pmu;
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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struct bcma_pflash pflash;
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int nr_serial_ports;
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struct bcma_serial_port serial_ports[4];
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#endif /* CONFIG_BCMA_DRIVER_MIPS */
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};
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/* Register access */
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51
include/linux/bcma/bcma_driver_mips.h
Normal file
51
include/linux/bcma/bcma_driver_mips.h
Normal file
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@ -0,0 +1,51 @@
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#ifndef LINUX_BCMA_DRIVER_MIPS_H_
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#define LINUX_BCMA_DRIVER_MIPS_H_
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#define BCMA_MIPS_IPSFLAG 0x0F08
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/* which sbflags get routed to mips interrupt 1 */
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#define BCMA_MIPS_IPSFLAG_IRQ1 0x0000003F
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#define BCMA_MIPS_IPSFLAG_IRQ1_SHIFT 0
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/* which sbflags get routed to mips interrupt 2 */
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#define BCMA_MIPS_IPSFLAG_IRQ2 0x00003F00
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#define BCMA_MIPS_IPSFLAG_IRQ2_SHIFT 8
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/* which sbflags get routed to mips interrupt 3 */
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#define BCMA_MIPS_IPSFLAG_IRQ3 0x003F0000
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#define BCMA_MIPS_IPSFLAG_IRQ3_SHIFT 16
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/* which sbflags get routed to mips interrupt 4 */
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#define BCMA_MIPS_IPSFLAG_IRQ4 0x3F000000
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#define BCMA_MIPS_IPSFLAG_IRQ4_SHIFT 24
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/* MIPS 74K core registers */
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#define BCMA_MIPS_MIPS74K_CORECTL 0x0000
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#define BCMA_MIPS_MIPS74K_EXCEPTBASE 0x0004
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#define BCMA_MIPS_MIPS74K_BIST 0x000C
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#define BCMA_MIPS_MIPS74K_INTMASK_INT0 0x0014
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#define BCMA_MIPS_MIPS74K_INTMASK(int) \
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((int) * 4 + BCMA_MIPS_MIPS74K_INTMASK_INT0)
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#define BCMA_MIPS_MIPS74K_NMIMASK 0x002C
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#define BCMA_MIPS_MIPS74K_GPIOSEL 0x0040
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#define BCMA_MIPS_MIPS74K_GPIOOUT 0x0044
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#define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
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#define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
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#define BCMA_MIPS_OOBSELOUTA30 0x100
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struct bcma_device;
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struct bcma_drv_mips {
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struct bcma_device *core;
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u8 setup_done:1;
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unsigned int assigned_irqs;
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};
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
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#else
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static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
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#endif
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extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
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extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
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#endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
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16
include/linux/bcma/bcma_soc.h
Normal file
16
include/linux/bcma/bcma_soc.h
Normal file
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@ -0,0 +1,16 @@
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#ifndef LINUX_BCMA_SOC_H_
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#define LINUX_BCMA_SOC_H_
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#include <linux/bcma/bcma.h>
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struct bcma_soc {
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struct bcma_bus bus;
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struct bcma_device core_cc;
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struct bcma_device core_mips;
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};
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int __init bcma_host_soc_register(struct bcma_soc *soc);
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int bcma_bus_register(struct bcma_bus *bus);
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#endif /* LINUX_BCMA_SOC_H_ */
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@ -161,6 +161,13 @@
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* @NL80211_CMD_SET_BEACON: set the beacon on an access point interface
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* using the %NL80211_ATTR_BEACON_INTERVAL, %NL80211_ATTR_DTIM_PERIOD,
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* %NL80211_ATTR_BEACON_HEAD and %NL80211_ATTR_BEACON_TAIL attributes.
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* Following attributes are provided for drivers that generate full Beacon
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* and Probe Response frames internally: %NL80211_ATTR_SSID,
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* %NL80211_ATTR_HIDDEN_SSID, %NL80211_ATTR_CIPHERS_PAIRWISE,
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* %NL80211_ATTR_CIPHER_GROUP, %NL80211_ATTR_WPA_VERSIONS,
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* %NL80211_ATTR_AKM_SUITES, %NL80211_ATTR_PRIVACY,
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* %NL80211_ATTR_AUTH_TYPE, %NL80211_ATTR_IE, %NL80211_ATTR_IE_PROBE_RESP,
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* %NL80211_ATTR_IE_ASSOC_RESP.
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* @NL80211_CMD_NEW_BEACON: add a new beacon to an access point interface,
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* parameters are like for %NL80211_CMD_SET_BEACON.
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* @NL80211_CMD_DEL_BEACON: remove the beacon, stop sending it
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@ -842,18 +849,20 @@ enum nl80211_commands {
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* @NL80211_ATTR_STATUS_CODE: StatusCode for the %NL80211_CMD_CONNECT
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* event (u16)
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* @NL80211_ATTR_PRIVACY: Flag attribute, used with connect(), indicating
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* that protected APs should be used.
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* that protected APs should be used. This is also used with NEW_BEACON to
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* indicate that the BSS is to use protection.
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*
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* @NL80211_ATTR_CIPHERS_PAIRWISE: Used with CONNECT and ASSOCIATE to
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* indicate which unicast key ciphers will be used with the connection
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* @NL80211_ATTR_CIPHERS_PAIRWISE: Used with CONNECT, ASSOCIATE, and NEW_BEACON
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* to indicate which unicast key ciphers will be used with the connection
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* (an array of u32).
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* @NL80211_ATTR_CIPHER_GROUP: Used with CONNECT and ASSOCIATE to indicate
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* which group key cipher will be used with the connection (a u32).
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* @NL80211_ATTR_WPA_VERSIONS: Used with CONNECT and ASSOCIATE to indicate
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* which WPA version(s) the AP we want to associate with is using
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* @NL80211_ATTR_CIPHER_GROUP: Used with CONNECT, ASSOCIATE, and NEW_BEACON to
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* indicate which group key cipher will be used with the connection (a
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* u32).
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* @NL80211_ATTR_WPA_VERSIONS: Used with CONNECT, ASSOCIATE, and NEW_BEACON to
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* indicate which WPA version(s) the AP we want to associate with is using
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* (a u32 with flags from &enum nl80211_wpa_versions).
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* @NL80211_ATTR_AKM_SUITES: Used with CONNECT and ASSOCIATE to indicate
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* which key management algorithm(s) to use (an array of u32).
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* @NL80211_ATTR_AKM_SUITES: Used with CONNECT, ASSOCIATE, and NEW_BEACON to
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* indicate which key management algorithm(s) to use (an array of u32).
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*
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* @NL80211_ATTR_REQ_IE: (Re)association request information elements as
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* sent out by the card, for ROAM and successful CONNECT events.
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|
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@ -1019,6 +1028,20 @@ enum nl80211_commands {
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* being a list of supported rates as defined by IEEE 802.11 7.3.2.2 but
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* without the length restriction (at most %NL80211_MAX_SUPP_RATES).
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*
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* @NL80211_ATTR_HIDDEN_SSID: indicates whether SSID is to be hidden from Beacon
|
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* and Probe Response (when response to wildcard Probe Request); see
|
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* &enum nl80211_hidden_ssid, represented as a u32
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*
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* @NL80211_ATTR_IE_PROBE_RESP: Information element(s) for Probe Response frame.
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* This is used with %NL80211_CMD_NEW_BEACON and %NL80211_CMD_SET_BEACON to
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* provide extra IEs (e.g., WPS/P2P IE) into Probe Response frames when the
|
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* driver (or firmware) replies to Probe Request frames.
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* @NL80211_ATTR_IE_ASSOC_RESP: Information element(s) for (Re)Association
|
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* Response frames. This is used with %NL80211_CMD_NEW_BEACON and
|
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* %NL80211_CMD_SET_BEACON to provide extra IEs (e.g., WPS/P2P IE) into
|
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* (Re)Association Response frames when the driver (or firmware) replies to
|
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* (Re)Association Request frames.
|
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*
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* @NL80211_ATTR_MAX: highest attribute number currently defined
|
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* @__NL80211_ATTR_AFTER_LAST: internal use
|
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*/
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@ -1224,6 +1247,11 @@ enum nl80211_attrs {
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NL80211_ATTR_SCAN_SUPP_RATES,
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NL80211_ATTR_HIDDEN_SSID,
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NL80211_ATTR_IE_PROBE_RESP,
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NL80211_ATTR_IE_ASSOC_RESP,
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/* add attributes here, update the policy in nl80211.c */
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__NL80211_ATTR_AFTER_LAST,
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|
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@ -2430,4 +2458,19 @@ enum nl80211_rekey_data {
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MAX_NL80211_REKEY_DATA = NUM_NL80211_REKEY_DATA - 1
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};
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/**
|
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* enum nl80211_hidden_ssid - values for %NL80211_ATTR_HIDDEN_SSID
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* @NL80211_HIDDEN_SSID_NOT_IN_USE: do not hide SSID (i.e., broadcast it in
|
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* Beacon frames)
|
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* @NL80211_HIDDEN_SSID_ZERO_LEN: hide SSID by using zero-length SSID element
|
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* in Beacon frames
|
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* @NL80211_HIDDEN_SSID_ZERO_CONTENTS: hide SSID by using correct length of SSID
|
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* element in Beacon frames but zero out each byte in the SSID
|
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*/
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enum nl80211_hidden_ssid {
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NL80211_HIDDEN_SSID_NOT_IN_USE,
|
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NL80211_HIDDEN_SSID_ZERO_LEN,
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NL80211_HIDDEN_SSID_ZERO_CONTENTS
|
||||
};
|
||||
|
||||
#endif /* __LINUX_NL80211_H */
|
||||
|
|
|
|||
|
|
@ -462,6 +462,46 @@
|
|||
#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
|
||||
#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
|
||||
|
||||
/* Values for boardflags_lo read from SPROM */
|
||||
#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
|
||||
#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
|
||||
#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
|
||||
#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
|
||||
#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
|
||||
#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
|
||||
#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
|
||||
#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
|
||||
#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
|
||||
#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
|
||||
#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
|
||||
#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
|
||||
#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
|
||||
#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
|
||||
#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
|
||||
#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
|
||||
|
||||
/* Values for boardflags_hi read from SPROM */
|
||||
#define SSB_BFH_NOPA 0x0001 /* has no PA */
|
||||
#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
|
||||
#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
|
||||
#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
|
||||
#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
|
||||
#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
|
||||
#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
|
||||
|
||||
/* Values for boardflags2_lo read from SPROM */
|
||||
#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
|
||||
#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
|
||||
#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
|
||||
#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
|
||||
#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
|
||||
#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
|
||||
#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
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#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
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||||
#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
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#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
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#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
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||||
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/* Values for SSB_SPROM1_BINF_CCODE */
|
||||
enum {
|
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SSB_SPROM1CCODE_WORLD = 0,
|
||||
|
|
|
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Loading…
Reference in a new issue