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[ARM] 4108/2: Allow multiple GIC interrupt controllers in a system

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The current implementation only assumes one GIC to be present in the
system. However, there are platforms with more than one cascaded interrupt
controllers (RealView/EB MPCore for example).

Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Catalin Marinas 2007-02-14 19:14:56 +01:00 • committed by Russell King
commit b3a1bde4db
4 changed files with 101 additions and 19 deletions
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5
include/asm-arm/hardware/gic.h
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@ -33,8 +33,9 @@
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
void gic_dist_init(void __iomem *base);
void gic_cpu_init(void __iomem *base);
void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
#endif