mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 13:44:26 -04:00
Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (98 commits) PCI PM: Put PM callbacks in the order of execution PCI PM: Run default PM callbacks for all devices using new framework PCI PM: Register power state of devices during initialization PCI PM: Call pci_fixup_device from legacy routines PCI PM: Rearrange code in pci-driver.c PCI PM: Avoid touching devices behind bridges in unknown state PCI PM: Move pci_has_legacy_pm_support PCI PM: Power-manage devices without drivers during suspend-resume PCI PM: Add suspend counterpart of pci_reenable_device PCI PM: Fix poweroff and restore callbacks PCI: Use msleep instead of cpu_relax during ASPM link retraining PCI: PCIe portdrv: Add kerneldoc comments to remining core funtions PCI: PCIe portdrv: Rearrange code so that related things are together PCI: PCIe portdrv: Fix suspend and resume of PCI Express port services PCI: PCIe portdrv: Add kerneldoc comments to some core functions x86/PCI: Do not use interrupt links for devices using MSI-X net: sfc: Use pci_clear_master() to disable bus mastering PCI: Add pci_clear_master() as opposite of pci_set_master() PCI hotplug: remove redundant test in cpq hotplug PCI: pciehp: cleanup register and field definitions ...
This commit is contained in:
Linus Torvalds
commit
b424e8d3b4
74 changed files with 2150 additions and 1332 deletions
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@ -49,6 +49,7 @@ struct resource_list {
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#define IORESOURCE_SIZEALIGN 0x00020000 /* size indicates alignment */
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#define IORESOURCE_STARTALIGN 0x00040000 /* start field is alignment */
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#define IORESOURCE_EXCLUSIVE 0x08000000 /* Userland may not map this resource */
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#define IORESOURCE_DISABLED 0x10000000
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#define IORESOURCE_UNSET 0x20000000
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#define IORESOURCE_AUTO 0x40000000
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@ -133,13 +134,16 @@ static inline unsigned long resource_type(struct resource *res)
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}
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/* Convenience shorthand with allocation */
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#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name))
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#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name))
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#define request_region(start,n,name) __request_region(&ioport_resource, (start), (n), (name), 0)
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#define __request_mem_region(start,n,name, excl) __request_region(&iomem_resource, (start), (n), (name), excl)
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#define request_mem_region(start,n,name) __request_region(&iomem_resource, (start), (n), (name), 0)
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#define request_mem_region_exclusive(start,n,name) \
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__request_region(&iomem_resource, (start), (n), (name), IORESOURCE_EXCLUSIVE)
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#define rename_region(region, newname) do { (region)->name = (newname); } while (0)
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extern struct resource * __request_region(struct resource *,
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resource_size_t start,
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resource_size_t n, const char *name);
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resource_size_t n, const char *name, int relaxed);
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/* Compatibility cruft */
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#define release_region(start,n) __release_region(&ioport_resource, (start), (n))
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@ -175,6 +179,7 @@ extern struct resource * __devm_request_region(struct device *dev,
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extern void __devm_release_region(struct device *dev, struct resource *parent,
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resource_size_t start, resource_size_t n);
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extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
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extern int iomem_is_exclusive(u64 addr);
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#endif /* __ASSEMBLY__ */
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#endif /* _LINUX_IOPORT_H */
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@ -8,6 +8,8 @@
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#ifndef _PCI_ACPI_H_
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#define _PCI_ACPI_H_
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#include <linux/acpi.h>
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#define OSC_QUERY_TYPE 0
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#define OSC_SUPPORT_TYPE 1
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#define OSC_CONTROL_TYPE 2
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@ -48,15 +50,7 @@
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#ifdef CONFIG_ACPI
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extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
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extern acpi_status __pci_osc_support_set(u32 flags, const char *hid);
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static inline acpi_status pci_osc_support_set(u32 flags)
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{
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return __pci_osc_support_set(flags, PCI_ROOT_HID_STRING);
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}
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static inline acpi_status pcie_osc_support_set(u32 flags)
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{
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return __pci_osc_support_set(flags, PCI_EXPRESS_ROOT_HID_STRING);
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}
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int pci_acpi_osc_support(acpi_handle handle, u32 flags);
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{
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/* Find root host bridge */
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@ -66,6 +60,15 @@ static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
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pdev->bus->number);
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}
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static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)
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{
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int seg = pci_domain_nr(pbus), busnr = pbus->number;
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struct pci_dev *bridge = pbus->self;
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if (bridge)
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return DEVICE_ACPI_HANDLE(&(bridge->dev));
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return acpi_get_pci_rootbridge_handle(seg, busnr);
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}
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#else
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#if !defined(AE_ERROR)
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typedef u32 acpi_status;
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@ -73,8 +76,6 @@ typedef u32 acpi_status;
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#endif
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static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
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{return AE_ERROR;}
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static inline acpi_status pci_osc_support_set(u32 flags) {return AE_ERROR;}
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static inline acpi_status pcie_osc_support_set(u32 flags) {return AE_ERROR;}
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static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
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{ return NULL; }
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#endif
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@ -82,7 +82,30 @@ enum pci_mmap_state {
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#define PCI_DMA_FROMDEVICE 2
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#define PCI_DMA_NONE 3
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#define DEVICE_COUNT_RESOURCE 12
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/*
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* For PCI devices, the region numbers are assigned this way:
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*/
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enum {
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/* #0-5: standard PCI resources */
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PCI_STD_RESOURCES,
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PCI_STD_RESOURCE_END = 5,
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/* #6: expansion ROM resource */
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PCI_ROM_RESOURCE,
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/* resources assigned to buses behind the bridge */
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#define PCI_BRIDGE_RESOURCE_NUM 4
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PCI_BRIDGE_RESOURCES,
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PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
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PCI_BRIDGE_RESOURCE_NUM - 1,
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/* total resources associated with a PCI device */
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PCI_NUM_RESOURCES,
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/* preserve this for compatibility */
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DEVICE_COUNT_RESOURCE
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};
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typedef int __bitwise pci_power_t;
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@ -274,18 +297,6 @@ static inline void pci_add_saved_cap(struct pci_dev *pci_dev,
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hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
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}
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/*
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* For PCI devices, the region numbers are assigned this way:
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*
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* 0-5 standard PCI regions
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* 6 expansion ROM
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* 7-10 bridges: address space assigned to buses behind the bridge
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*/
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#define PCI_ROM_RESOURCE 6
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#define PCI_BRIDGE_RESOURCES 7
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#define PCI_NUM_RESOURCES 11
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#ifndef PCI_BUS_NUM_RESOURCES
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#define PCI_BUS_NUM_RESOURCES 16
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#endif
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@ -325,6 +336,15 @@ struct pci_bus {
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#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
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#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
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#ifdef CONFIG_PCI_MSI
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static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
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{
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return pci_dev->msi_enabled || pci_dev->msix_enabled;
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}
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#else
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static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
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#endif
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/*
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* Error values that may be returned by PCI functions.
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*/
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@ -532,7 +552,9 @@ int __must_check pci_bus_add_device(struct pci_dev *dev);
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void pci_read_bridge_bases(struct pci_bus *child);
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struct resource *pci_find_parent_resource(const struct pci_dev *dev,
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struct resource *res);
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u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin);
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int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
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u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
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extern struct pci_dev *pci_dev_get(struct pci_dev *dev);
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extern void pci_dev_put(struct pci_dev *dev);
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extern void pci_remove_bus(struct pci_bus *b);
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@ -629,6 +651,7 @@ static inline int pci_is_managed(struct pci_dev *pdev)
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void pci_disable_device(struct pci_dev *dev);
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void pci_set_master(struct pci_dev *dev);
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void pci_clear_master(struct pci_dev *dev);
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int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
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#define HAVE_PCI_SET_MWI
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int __must_check pci_set_mwi(struct pci_dev *dev);
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@ -647,7 +670,7 @@ int pcie_get_readrq(struct pci_dev *dev);
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int pcie_set_readrq(struct pci_dev *dev, int rq);
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int pci_reset_function(struct pci_dev *dev);
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int pci_execute_reset_function(struct pci_dev *dev);
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void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
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void pci_update_resource(struct pci_dev *dev, int resno);
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int __must_check pci_assign_resource(struct pci_dev *dev, int i);
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int pci_select_bars(struct pci_dev *dev, unsigned long flags);
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@ -674,6 +697,11 @@ int pci_back_from_sleep(struct pci_dev *dev);
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/* Functions for PCI Hotplug drivers to use */
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int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
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/* Vital product data routines */
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ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
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ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
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int pci_vpd_truncate(struct pci_dev *dev, size_t size);
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/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
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void pci_bus_assign_resources(struct pci_bus *bus);
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void pci_bus_size_bridges(struct pci_bus *bus);
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@ -686,10 +714,13 @@ void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
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int (*)(struct pci_dev *, u8, u8));
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#define HAVE_PCI_REQ_REGIONS 2
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int __must_check pci_request_regions(struct pci_dev *, const char *);
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int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
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void pci_release_regions(struct pci_dev *);
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int __must_check pci_request_region(struct pci_dev *, int, const char *);
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int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
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void pci_release_region(struct pci_dev *, int);
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int pci_request_selected_regions(struct pci_dev *, int, const char *);
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int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
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void pci_release_selected_regions(struct pci_dev *, int);
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/* drivers/pci/bus.c */
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@ -779,6 +810,10 @@ static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev)
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static inline void pci_restore_msi_state(struct pci_dev *dev)
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{ }
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static inline int pci_msi_enabled(void)
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{
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return 0;
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}
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#else
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extern int pci_enable_msi(struct pci_dev *dev);
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extern void pci_msi_shutdown(struct pci_dev *dev);
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@ -789,6 +824,16 @@ extern void pci_msix_shutdown(struct pci_dev *dev);
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extern void pci_disable_msix(struct pci_dev *dev);
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extern void msi_remove_pci_irq_vectors(struct pci_dev *dev);
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extern void pci_restore_msi_state(struct pci_dev *dev);
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extern int pci_msi_enabled(void);
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#endif
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#ifndef CONFIG_PCIEASPM
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static inline int pcie_aspm_enabled(void)
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{
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return 0;
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}
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#else
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extern int pcie_aspm_enabled(void);
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#endif
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#ifdef CONFIG_HT_IRQ
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@ -1140,20 +1185,9 @@ static inline void pci_mmcfg_early_init(void) { }
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static inline void pci_mmcfg_late_init(void) { }
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#endif
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#ifdef CONFIG_HAS_IOMEM
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static inline void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
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{
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/*
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* Make sure the BAR is actually a memory resource, not an IO resource
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*/
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if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
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WARN_ON(1);
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return NULL;
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}
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return ioremap_nocache(pci_resource_start(pdev, bar),
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pci_resource_len(pdev, bar));
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}
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#endif
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int pci_ext_cfg_avail(struct pci_dev *dev);
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void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
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#endif /* __KERNEL__ */
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#endif /* LINUX_PCI_H */
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@ -228,6 +228,8 @@ extern acpi_status acpi_get_hp_params_from_firmware(struct pci_bus *bus,
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struct hotplug_params *hpp);
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int acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev, u32 flags);
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int acpi_root_bridge(acpi_handle handle);
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int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle);
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int acpi_pci_detect_ejectable(struct pci_bus *pbus);
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#endif
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#endif
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@ -210,6 +210,7 @@
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#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
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#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
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#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
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#define PCI_CAP_SIZEOF 4
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@ -316,6 +317,17 @@
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#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
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#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
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/* PCI Advanced Feature registers */
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#define PCI_AF_LENGTH 2
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#define PCI_AF_CAP 3
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#define PCI_AF_CAP_TP 0x01
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#define PCI_AF_CAP_FLR 0x02
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#define PCI_AF_CTRL 4
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#define PCI_AF_CTRL_FLR 0x01
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#define PCI_AF_STATUS 5
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#define PCI_AF_STATUS_TP 0x01
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/* PCI-X registers */
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#define PCI_X_CMD 2 /* Modes & Features */
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@ -399,20 +411,70 @@
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#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
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#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
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#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */
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#define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */
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#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
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#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
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#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
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#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
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#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
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#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
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#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */
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#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
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#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
|
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#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
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#define PCI_EXP_LNKCTL 16 /* Link Control */
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#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */
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#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */
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#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
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#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
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#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
|
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#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
|
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#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */
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#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */
|
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#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
|
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#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
|
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#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
|
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#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
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#define PCI_EXP_LNKSTA 18 /* Link Status */
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#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
|
||||
#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
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#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
|
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#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
|
||||
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
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#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
|
||||
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
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||||
#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
|
||||
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
|
||||
#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
|
||||
#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
|
||||
#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */
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#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */
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#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */
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#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
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#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
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#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */
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#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */
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#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */
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#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */
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#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
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#define PCI_EXP_SLTCTL 24 /* Slot Control */
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#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
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#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
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#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
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||||
#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
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#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
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#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
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||||
#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
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#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
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#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
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#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
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#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
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#define PCI_EXP_SLTSTA 26 /* Slot Status */
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||||
#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
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||||
#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
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||||
#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */
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||||
#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */
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||||
#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */
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||||
#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */
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||||
#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */
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||||
#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */
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||||
#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
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||||
#define PCI_EXP_RTCTL 28 /* Root Control */
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#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
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||||
#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
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|
|
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Loading…
Reference in a new issue