From b433f97c834d5c486dcf3e67aa97ca079b9481e5 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Mon, 7 Sep 2020 12:28:48 +0530 Subject: [PATCH] ARM: dts: msm: Add UFS support for SA6155 Add UFS host controller and UFS PHY (attached to embedded UFS card) for SA6155 platform. Change-Id: Ic75617e3d8eb406f876cc71c8931bcfee545438d --- qcom/sa6155-adp-air.dtsi | 28 +++++++++ qcom/sa6155-adp-star.dtsi | 28 +++++++++ qcom/sm6150.dtsi | 118 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) diff --git a/qcom/sa6155-adp-air.dtsi b/qcom/sa6155-adp-air.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-air.dtsi +++ b/qcom/sa6155-adp-air.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sa6155-adp-star.dtsi b/qcom/sa6155-adp-star.dtsi index 91c1ac0cdf99..36c1103f0315 100644 --- a/qcom/sa6155-adp-star.dtsi +++ b/qcom/sa6155-adp-star.dtsi @@ -1 +1,29 @@ #include "sa6155-adp-common.dtsi" + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v3-660"; + + vdda-phy-supply = <&pm6155_1_l5>; /* 0.9v */ + vdda-pll-supply = <&pm6155_1_l12>; + vdda-phy-max-microamp = <30000>; + vdda-pll-max-microamp = <12000>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm6155_1_l17>; + vcc-voltage-level = <2950000 2960000>; + vccq2-supply = <&pm6155_1_s4>; + vcc-max-microamp = <800000>; + vccq2-max-microamp = <600000>; + + qcom,vddp-ref-clk-supply = <&pm6155_1_l11>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vddp-ref-clk-min-uV = <1232000>; + qcom,vddp-ref-clk-max-uV = <1260000>; + + status = "ok"; +}; diff --git a/qcom/sm6150.dtsi b/qcom/sm6150.dtsi index b8ed48c57741..8e8abca5d5e6 100644 --- a/qcom/sm6150.dtsi +++ b/qcom/sm6150.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ memory { device_type = "memory"; reg = <0 0 0 0>; }; aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS slot */ serial0 = &qupv3_se0_2uart; }; @@ -1045,6 +1047,122 @@ #interconnect-cells = <1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; /* PHY regs */ + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <1>; + + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufshc_mem 0>; + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>, + <0x1d90000 0x8000>; + reg-names = "ufs_mem", "ufs_ice"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <1>; + limit-phy-submode = <0>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + spm-level = <5>; + + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <12>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "MAX"; + + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + non-removable; + + status = "disabled"; + qos0 { + mask = <0xc0>; + vote = <67>; + }; + + qos1 { + mask = <0x3f>; + vote = <67>; + }; + }; + qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;