From b49809f9d8834616c325e6498e9fe6cc62ecdf16 Mon Sep 17 00:00:00 2001
From: Hemant Kumar <hemantk@quicinc.com>
Date: Mon, 29 Mar 2021 20:34:20 -0700
Subject: [PATCH] ARM: dts: msm: Add child node entry for CPE NTN3 i2c client
 on sdxlemur

In order to access NTN3 switch registers add i2c client properties.
By accessing these registers, root complex driver can toggle NTN3
GPIOs tied to downstream endpoint reset. i2c interface is also used
to dump NTN3 registers for debugging PCIe link related issues.

Change-Id: Ib7e85c463a0072dd2919559ab4d701d5eb42f400
---
 qcom/sdxlemur-mtp-cpe.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi
index 165cb7c5594c..e63b48f2a73d 100644
--- a/qcom/sdxlemur-mtp-cpe.dtsi
+++ b/qcom/sdxlemur-mtp-cpe.dtsi
@@ -35,7 +35,22 @@
 	};
 };
 
+&i2c_5 {
+	status = "ok";
+
+	pcie_i2c_ctrl: pcie_i2c_ctrl {
+		compatible = "qcom,pcie0-i2c-ntn3";
+		reg = <0x77>;
+		gpio-config-reg = <0x801208>;
+		ep-reset-reg = <0x801210>;
+		ep-reset-gpio-mask = <0xf>;
+		dump-regs = <0x801330 0x801350 0x801370>;
+	};
+};
+
 &pcie0 {
+	pcie-i2c-phandle = <&i2c_5>;
+
 	vreg-3p3-supply = <&aqr_vreg>;
 
 	iommu-map = <0x0 &apps_smmu 0x0200 0x1>,