A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-14 08:36:12 -04:00
Code Issues Projects Releases Packages Wiki Activity

ARM: dts: msm: Add cpufreq HW device node SM6150

Browse source 
Add cpufreq HW device node to scale 6 domain-0 & 2 domain-1 cores
on SM6150 SoCs.

Change-Id: I8da676df93afabb9820e4a270e9cb401658152de
This commit is contained in:
Veera Vegivada 2020-09-03 11:02:41 +05:30 • committed by Gerrit - the friendly Code Review server
commit b4a0015b77
1 changed files with 17 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

17
qcom/sm6150.dtsi
View file

@ -36,6 +36,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@ -74,6 +75,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "arm,arch-cache";
@ -107,6 +109,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "arm,arch-cache";
@ -139,6 +142,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "arm,arch-cache";
@ -171,6 +175,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "arm,arch-cache";
@ -203,6 +208,7 @@
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "arm,arch-cache";
@ -235,6 +241,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x10000>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "arm,arch-cache";
@ -276,6 +283,7 @@
capacity-dmips-mhz = <1740>;
cache-size = <0x10000>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "arm,arch-cache";
@ -862,6 +870,15 @@
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <2>;
};
};
#include "sm6150-qupv3.dtsi"