mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
ARM: SoC platform changes for 3.12
This branch contains mostly additions and changes to platform enablement
and SoC-level drivers. Since there's sometimes a dependency on device-tree
changes, there's also a fair amount of those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving
MSI arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers.
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Olof Johansson:
"This branch contains mostly additions and changes to platform
enablement and SoC-level drivers. Since there's sometimes a
dependency on device-tree changes, there's also a fair amount of
those in this branch.
Pieces worth mentioning are:
- Mbus driver for Marvell platforms, allowing kernel configuration
and resource allocation of on-chip peripherals.
- Enablement of the mbus infrastructure from Marvell PCI-e drivers.
- Preparation of MSI support for Marvell platforms.
- Addition of new PCI-e host controller driver for Tegra platforms
- Some churn caused by sharing of macro names between i.MX 6Q and 6DL
platforms in the device tree sources and header files.
- Various suspend/PM updates for Tegra, including LP1 support.
- Versatile Express support for MCPM, part of big little support.
- Allwinner platform support for A20 and A31 SoCs (dual and quad
Cortex-A7)
- OMAP2+ support for DRA7, a new Cortex-A15-based SoC.
The code that touches other architectures are patches moving MSI
arch-specific functions over to weak symbols and removal of
ARCH_SUPPORTS_MSI, acked by PCI maintainers"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
...
This commit is contained in:
Linus Torvalds
commit
b4b50fd78b
288 changed files with 12546 additions and 6424 deletions
|
|
@ -59,3 +59,6 @@ Boards:
|
|||
|
||||
- AM43x EPOS EVM
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||||
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
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- DRA7 EVM: Software Developement Board for DRA7XX
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compatible = "ti,dra7-evm", "ti,dra7"
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|
|
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|||
33
Documentation/devicetree/bindings/arm/vexpress-scc.txt
Normal file
33
Documentation/devicetree/bindings/arm/vexpress-scc.txt
Normal file
|
|
@ -0,0 +1,33 @@
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ARM Versatile Express Serial Configuration Controller
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-----------------------------------------------------
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Test chips for ARM Versatile Express platform implement SCC (Serial
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Configuration Controller) interface, used to set initial conditions
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for the test chip.
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In some cases its registers are also mapped in normal address space
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and can be used to obtain runtime information about the chip internals
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(like silicon temperature sensors) and as interface to other subsystems
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like platform configuration control and power management.
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Required properties:
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- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
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where <model> is the full tile model name (as used
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in the tile's Technical Reference Manual),
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eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
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compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
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Optional properties:
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- reg: when the SCC is memory mapped, physical address and size of the
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registers window
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- interrupts: when the SCC can generate a system-level interrupt
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Example:
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scc@7fff0000 {
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compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
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reg = <0 0x7fff0000 0 0x1000>;
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interrupts = <0 95 4>;
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};
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@ -8,7 +8,7 @@ The actual devices are instantiated from the child nodes of a WEIM node.
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Required properties:
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- compatible: Should be set to "fsl,imx6q-weim"
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- compatible: Should be set to "fsl,<soc>-weim"
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- reg: A resource specifier for the register space
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(see the example below)
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- clocks: the clock, see the example below.
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@ -21,11 +21,18 @@ Required properties:
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains 6 timing values for the
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- fsl,weim-cs-timing: The timing array, contains timing values for the
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child node. We can get the CS index from the child
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node's "reg" property. This property contains the values
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for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
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EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
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node's "reg" property. The number of registers depends
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on the selected chip.
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For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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registers: CSxU, CSxL.
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For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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there are three registers: CSCRxU, CSCRxL, CSCRxA.
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For i.MX50, i.MX53 ("fsl,imx50-weim"),
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i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
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there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
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CSxRCR2, CSxWCR1, CSxWCR2.
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Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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|
|
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276
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
Normal file
276
Documentation/devicetree/bindings/bus/mvebu-mbus.txt
Normal file
|
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@ -0,0 +1,276 @@
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* Marvell MBus
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Required properties:
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- compatible: Should be set to one of the following:
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,kirkwood-mbus
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marvell,dove-mbus
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marvell,orion5x-88f5281-mbus
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marvell,orion5x-88f5182-mbus
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marvell,orion5x-88f5181-mbus
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marvell,orion5x-88f6183-mbus
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marvell,mv78xx0-mbus
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- address-cells: Must be '2'. The first cell for the MBus ID encoding,
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the second cell for the address offset within the window.
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|
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- size-cells: Must be '1'.
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- ranges: Must be set up to provide a proper translation for each child.
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See the examples below.
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- controller: Contains a single phandle referring to the MBus controller
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node. This allows to specify the node that contains the
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registers that control the MBus, which is typically contained
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within the internal register window (see below).
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Optional properties:
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- pcie-mem-aperture: This optional property contains the aperture for
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the memory region of the PCIe driver.
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If it's defined, it must encode the base address and
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size for the address decoding windows allocated for
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the PCIe memory region.
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- pcie-io-aperture: Just as explained for the above property, this
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optional property contains the aperture for the
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I/O region of the PCIe driver.
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* Marvell MBus controller
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Required properties:
|
||||
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- compatible: Should be set to "marvell,mbus-controller".
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|
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- reg: Device's register space.
|
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Two entries are expected (see the examples below):
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the first one controls the devices decoding window and
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the second one controls the SDRAM decoding window.
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Example:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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internal-regs {
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compatible = "simple-bus";
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* more children ...*/
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};
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};
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** MBus address decoding window specification
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The MBus children address space is comprised of two cells: the first one for
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the window ID and the second one for the offset within the window.
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In order to allow to describe valid and non-valid window entries, the
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following encoding is used:
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0xSIAA0000 0x00oooooo
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Where:
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|
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S = 0x0 for a MBus valid window
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S = 0xf for a non-valid window (see below)
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|
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If S = 0x0, then:
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I = 4-bit window target ID
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AA = windpw attribute
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|
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If S = 0xf, then:
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I = don't care
|
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AA = 1 for internal register
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|
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Following the above encoding, for each ranges entry for a MBus valid window
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(S = 0x0), an address decoding window is allocated. On the other side,
|
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entries for translation that do not correspond to valid windows (S = 0xf)
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are skipped.
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = <0xf0010000 0 0 0xd0000000 0x100000
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0x01e00000 0 0 0xfff00000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <0x01e00000 0 0x100000>;
|
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};
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/* other children */
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...
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internal-regs {
|
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compatible = "simple-bus";
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ranges = <0 0xf0010000 0 0x100000>;
|
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|
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mbusc: mbus-controller@20000 {
|
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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|
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/* more children ...*/
|
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};
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};
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In the shown example, the translation entry in the 'ranges' property is what
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makes the MBus driver create a static decoding window for the corresponding
|
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given child device. Note that the binding does not require child nodes to be
|
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present. Of course, child nodes are needed to probe the devices.
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|
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Since each window is identified by its target ID and attribute ID there's
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a special macro that can be use to simplify the translation entries:
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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|
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Using this macro, the above example would be:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
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|
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bootrom {
|
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
|
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};
|
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|
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/* other children */
|
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...
|
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|
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internal-regs {
|
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compatible = "simple-bus";
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#address-cells = <1>;
|
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#size-cells = <1>;
|
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
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|
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mbusc: mbus-controller@20000 {
|
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compatible = "marvell,mbus-controller";
|
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reg = <0x20000 0x100>, <0x20180 0x20>;
|
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};
|
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|
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/* other children */
|
||||
...
|
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};
|
||||
};
|
||||
|
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|
||||
** About the window base address
|
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|
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Remember the MBus controller allows a great deal of flexibility for choosing
|
||||
the decoding window base address. When planning the device tree layout it's
|
||||
possible to choose any address as the base address, provided of course there's
|
||||
a region large enough available, and with the required alignment.
|
||||
|
||||
Yet in other words: there's nothing preventing us from setting a base address
|
||||
of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
|
||||
unused.
|
||||
|
||||
** Window allocation policy
|
||||
|
||||
The mbus-node ranges property defines a set of mbus windows that are expected
|
||||
to be set by the operating system and that are guaranteed to be free of overlaps
|
||||
with one another or with the system memory ranges.
|
||||
|
||||
Each entry in the property refers to exactly one window. If the operating system
|
||||
choses to use a different set of mbus windows, it must ensure that any address
|
||||
translations performed from downstream devices are adapted accordingly.
|
||||
|
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The operating system may insert additional mbus windows that do not conflict
|
||||
with the ones listed in the ranges, e.g. for mapping PCIe devices.
|
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As a special case, the internal register window must be set up by the boot
|
||||
loader at the address listed in the ranges property, since access to that region
|
||||
is needed to set up the other windows.
|
||||
|
||||
** Example
|
||||
|
||||
See the example below, where a more complete device tree is shown:
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armadaxp-mbus", "simple-bus";
|
||||
controller = <&mbusc>;
|
||||
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
|
||||
|
||||
/* NOR */
|
||||
nor {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "okay";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
|
||||
0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
|
||||
|
||||
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
interrupt-controller@20000 {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -197,6 +197,7 @@ clocks and IDs.
|
|||
spdif0_gate 183
|
||||
spdif1_gate 184
|
||||
spdif_ipg_gate 185
|
||||
ocram 186
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
|
|
|
|||
|
|
@ -209,6 +209,12 @@ clocks and IDs.
|
|||
pll5_post_div 194
|
||||
pll5_video_div 195
|
||||
eim_slow 196
|
||||
spdif 197
|
||||
cko2_sel 198
|
||||
cko2_podf 199
|
||||
cko2 200
|
||||
cko 201
|
||||
vdoa 202
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
* Marvell EBU PCIe interfaces
|
||||
|
||||
Mandatory properties:
|
||||
|
||||
- compatible: one of the following values:
|
||||
marvell,armada-370-pcie
|
||||
marvell,armada-xp-pcie
|
||||
|
|
@ -10,11 +11,49 @@ Mandatory properties:
|
|||
- #interrupt-cells, set to <1>
|
||||
- bus-range: PCI bus numbers covered
|
||||
- device_type, set to "pci"
|
||||
- ranges: ranges for the PCI memory and I/O regions, as well as the
|
||||
MMIO registers to control the PCIe interfaces.
|
||||
- ranges: ranges describing the MMIO registers to control the PCIe
|
||||
interfaces, and ranges describing the MBus windows needed to access
|
||||
the memory and I/O regions of each PCIe interface.
|
||||
|
||||
In addition, the Device Tree node must have sub-nodes describing each
|
||||
The ranges describing the MMIO registers have the following layout:
|
||||
|
||||
0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
|
||||
|
||||
where:
|
||||
|
||||
* r is a 32-bits value that gives the offset of the MMIO
|
||||
registers of this PCIe interface, from the base of the internal
|
||||
registers.
|
||||
|
||||
* s is a 32-bits value that give the size of this MMIO
|
||||
registers area. This range entry translates the '0x82000000 0 r' PCI
|
||||
address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
|
||||
of the internal register window (as identified by MBUS_ID(0xf0,
|
||||
0x01)).
|
||||
|
||||
The ranges describing the MBus windows have the following layout:
|
||||
|
||||
0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
|
||||
|
||||
where:
|
||||
|
||||
* t is the type of the MBus window (as defined by the standard PCI DT
|
||||
bindings), 1 for I/O and 2 for memory.
|
||||
|
||||
* s is the PCI slot that corresponds to this PCIe interface
|
||||
|
||||
* w is the 'target ID' value for the MBus window
|
||||
|
||||
* a the 'attribute' value for the MBus window.
|
||||
|
||||
Since the location and size of the different MBus windows is not fixed in
|
||||
hardware, and only determined in runtime, those ranges cover the full first
|
||||
4 GB of the physical address space, and do not translate into a valid CPU
|
||||
address.
|
||||
|
||||
In addition, the device tree node must have sub-nodes describing each
|
||||
PCIe interface, having the following mandatory properties:
|
||||
|
||||
- reg: used only for interrupt mapping, so only the first four bytes
|
||||
are used to refer to the correct bus number and device number.
|
||||
- assigned-addresses: reference to the MMIO registers used to control
|
||||
|
|
@ -26,7 +65,8 @@ PCIe interface, having the following mandatory properties:
|
|||
- #address-cells, set to <3>
|
||||
- #size-cells, set to <2>
|
||||
- #interrupt-cells, set to <1>
|
||||
- ranges, empty property.
|
||||
- ranges, translating the MBus windows ranges of the parent node into
|
||||
standard PCI addresses.
|
||||
- interrupt-map-mask and interrupt-map, standard PCI properties to
|
||||
define the mapping of the PCIe interface to interrupt numbers.
|
||||
|
||||
|
|
@ -47,27 +87,50 @@ pcie-controller {
|
|||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
|
||||
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
|
@ -78,12 +141,13 @@ pcie-controller {
|
|||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
|
@ -94,12 +158,13 @@ pcie-controller {
|
|||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
|
@ -110,12 +175,13 @@ pcie-controller {
|
|||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
|
|
@ -126,12 +192,13 @@ pcie-controller {
|
|||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
|
@ -142,12 +209,13 @@ pcie-controller {
|
|||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
|
@ -158,12 +226,13 @@ pcie-controller {
|
|||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
|
@ -174,12 +243,13 @@ pcie-controller {
|
|||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
|
|
@ -187,14 +257,16 @@ pcie-controller {
|
|||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
|
|
@ -205,12 +277,13 @@ pcie-controller {
|
|||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
|
|
|
|||
163
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
Normal file
163
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
NVIDIA Tegra PCIe controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
|
||||
- device_type: Must be "pci"
|
||||
- reg: A list of physical base address and length for each set of controller
|
||||
registers. Must contain an entry for each entry in the reg-names property.
|
||||
- reg-names: Must include the following entries:
|
||||
"pads": PADS registers
|
||||
"afi": AFI registers
|
||||
"cs": configuration space region
|
||||
- interrupts: A list of interrupt outputs of the controller. Must contain an
|
||||
entry for each entry in the interrupt-names property.
|
||||
- interrupt-names: Must include the following entries:
|
||||
"intr": The Tegra interrupt that is asserted for controller interrupts
|
||||
"msi": The Tegra interrupt that is asserted when an MSI is received
|
||||
- pex-clk-supply: Supply voltage for internal reference clock
|
||||
- vdd-supply: Power supply for controller (1.05V)
|
||||
- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
|
||||
- bus-range: Range of bus numbers associated with this controller
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- cell 0 specifies the bus and device numbers of the root port:
|
||||
[23:16]: bus number
|
||||
[15:11]: device number
|
||||
- cell 1 denotes the upper 32 address bits and should be 0
|
||||
- cell 2 contains the lower 32 address bits and is used to translate to the
|
||||
CPU address space
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
- ranges: Describes the translation of addresses for root ports and standard
|
||||
PCI regions. The entries must be 6 cells each, where the first three cells
|
||||
correspond to the address as described for the #address-cells property
|
||||
above, the fourth cell is the physical CPU address to translate to and the
|
||||
fifth and six cells are as described for the #size-cells property above.
|
||||
- The first two entries are expected to translate the addresses for the root
|
||||
port registers, which are referenced by the assigned-addresses property of
|
||||
the root port nodes (see below).
|
||||
- The remaining entries setup the mapping for the standard I/O, memory and
|
||||
prefetchable PCI regions. The first cell determines the type of region
|
||||
that is setup:
|
||||
- 0x81000000: I/O memory region
|
||||
- 0x82000000: non-prefetchable memory region
|
||||
- 0xc2000000: prefetchable memory region
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- clocks: List of clock inputs of the controller. Must contain an entry for
|
||||
each entry in the clock-names property.
|
||||
- clock-names: Must include the following entries:
|
||||
"pex": The Tegra clock of that name
|
||||
"afi": The Tegra clock of that name
|
||||
"pcie_xclk": The Tegra clock of that name
|
||||
"pll_e": The Tegra clock of that name
|
||||
"cml": The Tegra clock of that name (not required for Tegra20)
|
||||
|
||||
Root ports are defined as subnodes of the PCIe controller node.
|
||||
|
||||
Required properties:
|
||||
- device_type: Must be "pci"
|
||||
- assigned-addresses: Address and size of the port configuration registers
|
||||
- reg: PCI bus address of the root port
|
||||
- #address-cells: Must be 3
|
||||
- #size-cells: Must be 2
|
||||
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
|
||||
property is sufficient.
|
||||
- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
|
||||
are:
|
||||
- Root port 0 uses 4 lanes, root port 1 is unused.
|
||||
- Both root ports use 2 lanes.
|
||||
|
||||
Example:
|
||||
|
||||
SoC DTSI:
|
||||
|
||||
pcie-controller {
|
||||
compatible = "nvidia,tegra20-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0x80003000 0x00000800 /* PADS registers */
|
||||
0x80003800 0x00000200 /* AFI registers */
|
||||
0x90000000 0x10000000>; /* configuration space */
|
||||
reg-names = "pads", "afi", "cs";
|
||||
interrupts = <0 98 0x04 /* controller interrupt */
|
||||
0 99 0x04>; /* MSI interrupt */
|
||||
interrupt-names = "intr", "msi";
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
|
||||
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
|
||||
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
|
||||
0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
|
||||
|
||||
clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
|
||||
<&tegra_car 118>;
|
||||
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
|
||||
status = "disabled";
|
||||
|
||||
pci@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
|
||||
reg = <0x000800 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
|
||||
pci@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
|
||||
reg = <0x001000 0 0 0 0>;
|
||||
status = "disabled";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges;
|
||||
|
||||
nvidia,num-lanes = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Board DTS:
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
vdd-supply = <&pci_vdd_reg>;
|
||||
pex-clk-supply = <&pci_clk_reg>;
|
||||
|
||||
/* root port 00:01.0 */
|
||||
pci@1,0 {
|
||||
status = "okay";
|
||||
|
||||
/* bridge 01:00.0 (optional) */
|
||||
pci@0,0 {
|
||||
reg = <0x010000 0 0 0 0>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
/* endpoint 02:00.0 */
|
||||
pci@0,0 {
|
||||
reg = <0x020000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Note that devices on the PCI bus are dynamically discovered using PCI's bus
|
||||
enumeration and therefore don't need corresponding device nodes in DT. However
|
||||
if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
|
||||
device nodes need to be added in order to allow the bus' children to be
|
||||
instantiated at the proper location in the operating system's device tree (as
|
||||
illustrated by the optional nodes in the example above).
|
||||
|
|
@ -1,8 +1,9 @@
|
|||
Allwinner sun4i Watchdog timer
|
||||
Allwinner SoCs Watchdog timer
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : should be "allwinner,sun4i-wdt"
|
||||
- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
|
||||
SoC families being sun4i and sun6i
|
||||
- reg : Specifies base physical address and size of the registers.
|
||||
|
||||
Example:
|
||||
Loading…
Reference in a new issue