mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 03:01:39 -04:00
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (278 commits) arm: remove machine_desc.io_pg_offst and .phys_io arm: use addruart macro to establish debug mappings arm: return both physical and virtual addresses from addruart arm/debug: consolidate addruart macros for CONFIG_DEBUG_ICEDCC ARM: make struct machine_desc definition coherent with its comment eukrea_mbimxsd-baseboard: Pass the correct GPIO to gpio_free cpuimx27: fix compile when ULPI is selected mach-pcm037_eet: fix compile errors Fixing ethernet driver compilation error for i.MX31 ADS board cpuimx51: update board support mx5: add cpuimx51sd module and its baseboard iomux-mx51: fix GPIO_1_xx 's IOMUX configuration imx-esdhc: update devices registration mx51: add resources for SD/MMC on i.MX51 iomux-mx51: fix SD1 and SD2's iomux configuration clock-mx51: rename CLOCK1 to CLOCK_CCGR for better readability clock-mx51: factorize clk_set_parent and clk_get_rate eukrea_mbimxsd: add support for DVI displays cpuimx25 & cpuimx35: fix OTG port registration in host mode i.MX31 and i.MX35 : fix errate TLSbo65953 and ENGcm09472 ...
This commit is contained in:
Linus Torvalds
commit
b5153163ed
844 changed files with 25244 additions and 6688 deletions
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@ -143,10 +143,26 @@ config SPI_GPIO
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GPIO operations, you should be able to leverage that for better
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speed with a custom version of this driver; see the source code.
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config SPI_IMX_VER_IMX1
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def_bool y if SOC_IMX1
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config SPI_IMX_VER_0_0
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def_bool y if SOC_IMX21 || SOC_IMX27
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config SPI_IMX_VER_0_4
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def_bool y if ARCH_MX31
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config SPI_IMX_VER_0_7
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def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51
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config SPI_IMX_VER_2_3
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def_bool y if ARCH_MX51
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config SPI_IMX
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tristate "Freescale i.MX SPI controllers"
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depends on ARCH_MXC
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select SPI_BITBANG
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default m if IMX_HAVE_PLATFORM_SPI_IMX
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help
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This enables using the Freescale i.MX SPI controllers in master
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mode.
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@ -56,7 +56,28 @@ struct spi_imx_config {
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unsigned int speed_hz;
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unsigned int bpw;
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unsigned int mode;
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int cs;
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u8 cs;
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};
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enum spi_imx_devtype {
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SPI_IMX_VER_IMX1,
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SPI_IMX_VER_0_0,
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SPI_IMX_VER_0_4,
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SPI_IMX_VER_0_5,
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SPI_IMX_VER_0_7,
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SPI_IMX_VER_2_3,
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SPI_IMX_VER_AUTODETECT,
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};
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struct spi_imx_data;
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struct spi_imx_devtype_data {
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void (*intctrl)(struct spi_imx_data *, int);
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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void (*trigger)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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void (*reset)(struct spi_imx_data *);
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unsigned int fifosize;
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};
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struct spi_imx_data {
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@ -76,11 +97,7 @@ struct spi_imx_data {
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const void *tx_buf;
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unsigned int txfifo; /* number of words pushed in tx FIFO */
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/* SoC specific functions */
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void (*intctrl)(struct spi_imx_data *, int);
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int (*config)(struct spi_imx_data *, struct spi_imx_config *);
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void (*trigger)(struct spi_imx_data *);
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int (*rx_available)(struct spi_imx_data *);
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struct spi_imx_devtype_data devtype_data;
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};
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#define MXC_SPI_BUF_RX(type) \
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@ -140,7 +157,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
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return max;
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}
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/* MX1, MX31, MX35 */
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/* MX1, MX31, MX35, MX51 CSPI */
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static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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unsigned int fspi)
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{
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@ -155,6 +172,128 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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return 7;
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}
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#define SPI_IMX2_3_CTRL 0x08
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#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
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#define SPI_IMX2_3_CTRL_XCH (1 << 2)
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#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
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#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
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#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
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#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
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#define SPI_IMX2_3_CTRL_BL_OFFSET 20
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#define SPI_IMX2_3_CONFIG 0x0c
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#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define SPI_IMX2_3_INT 0x10
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#define SPI_IMX2_3_INT_TEEN (1 << 0)
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#define SPI_IMX2_3_INT_RREN (1 << 3)
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#define SPI_IMX2_3_STAT 0x18
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#define SPI_IMX2_3_STAT_RR (1 << 3)
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/* MX51 eCSPI */
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static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi)
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{
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/*
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* there are two 4-bit dividers, the pre-divider divides by
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* $pre, the post-divider by 2^$post
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*/
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unsigned int pre, post;
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if (unlikely(fspi > fin))
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return 0;
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post = fls(fin) - fls(fspi);
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if (fin > fspi << post)
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post++;
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/* now we have: (fin <= fspi << post) with post being minimal */
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post = max(4U, post) - 4;
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if (unlikely(post > 0xf)) {
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pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
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__func__, fspi, fin);
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return 0xff;
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}
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pre = DIV_ROUND_UP(fin, fspi << post) - 1;
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pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
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__func__, fin, fspi, post, pre);
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return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) |
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(post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET);
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}
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static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned val = 0;
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if (enable & MXC_INT_TE)
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val |= SPI_IMX2_3_INT_TEEN;
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if (enable & MXC_INT_RR)
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val |= SPI_IMX2_3_INT_RREN;
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writel(val, spi_imx->base + SPI_IMX2_3_INT);
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}
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static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx)
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{
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u32 reg;
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reg = readl(spi_imx->base + SPI_IMX2_3_CTRL);
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reg |= SPI_IMX2_3_CTRL_XCH;
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writel(reg, spi_imx->base + SPI_IMX2_3_CTRL);
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}
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static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
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/* set master mode */
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ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);
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/* set clock speed */
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ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
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/* set chip select to use */
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ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);
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ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;
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cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);
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if (config->mode & SPI_CPHA)
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cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);
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if (config->mode & SPI_CPOL)
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cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);
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if (config->mode & SPI_CS_HIGH)
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cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);
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writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
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writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);
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return 0;
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}
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static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx)
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{
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return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR;
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}
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static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx)
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{
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/* drain receive buffer */
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while (spi_imx2_3_rx_available(spi_imx))
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readl(spi_imx->base + MXC_CSPIRXDATA);
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}
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#define MX31_INTREG_TEEN (1 << 0)
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#define MX31_INTREG_RREN (1 << 3)
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@ -178,7 +317,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
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* the i.MX35 has a slightly different register layout for bits
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* we do not use here.
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*/
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static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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{
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unsigned int val = 0;
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@ -190,7 +329,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
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writel(val, spi_imx->base + MXC_CSPIINT);
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}
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static void mx31_trigger(struct spi_imx_data *spi_imx)
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static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
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{
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unsigned int reg;
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@ -199,20 +338,16 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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}
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static int mx31_config(struct spi_imx_data *spi_imx,
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static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX31_CSPICTRL_DR_SHIFT;
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if (cpu_is_mx31())
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reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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else if (cpu_is_mx25() || cpu_is_mx35()) {
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reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
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reg |= MX31_CSPICTRL_SSCTL;
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}
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reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
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if (config->mode & SPI_CPHA)
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reg |= MX31_CSPICTRL_PHA;
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@ -220,23 +355,52 @@ static int mx31_config(struct spi_imx_data *spi_imx,
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reg |= MX31_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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reg |= MX31_CSPICTRL_SSPOL;
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if (config->cs < 0) {
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if (cpu_is_mx31())
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reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
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else if (cpu_is_mx25() || cpu_is_mx35())
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reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
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}
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if (cs < 0)
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reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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return 0;
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}
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static int mx31_rx_available(struct spi_imx_data *spi_imx)
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static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
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struct spi_imx_config *config)
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{
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unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
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int cs = spi_imx->chipselect[config->cs];
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reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
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MX31_CSPICTRL_DR_SHIFT;
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reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
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reg |= MX31_CSPICTRL_SSCTL;
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if (config->mode & SPI_CPHA)
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reg |= MX31_CSPICTRL_PHA;
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if (config->mode & SPI_CPOL)
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reg |= MX31_CSPICTRL_POL;
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if (config->mode & SPI_CS_HIGH)
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reg |= MX31_CSPICTRL_SSPOL;
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if (cs < 0)
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reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
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writel(reg, spi_imx->base + MXC_CSPICTRL);
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return 0;
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}
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static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
|
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{
|
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return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
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}
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static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
|
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{
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/* drain receive buffer */
|
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while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
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readl(spi_imx->base + MXC_CSPIRXDATA);
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}
|
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|
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#define MX27_INTREG_RR (1 << 4)
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#define MX27_INTREG_TEEN (1 << 9)
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#define MX27_INTREG_RREN (1 << 13)
|
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|
|
@ -250,7 +414,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
|
|||
#define MX27_CSPICTRL_DR_SHIFT 14
|
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#define MX27_CSPICTRL_CS_SHIFT 19
|
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|
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static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
|
||||
static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
|
||||
{
|
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unsigned int val = 0;
|
||||
|
||||
|
|
@ -262,7 +426,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|||
writel(val, spi_imx->base + MXC_CSPIINT);
|
||||
}
|
||||
|
||||
static void mx27_trigger(struct spi_imx_data *spi_imx)
|
||||
static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
|
|
@ -271,10 +435,11 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
|
|||
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
||||
}
|
||||
|
||||
static int mx27_config(struct spi_imx_data *spi_imx,
|
||||
static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
|
||||
struct spi_imx_config *config)
|
||||
{
|
||||
unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
|
||||
int cs = spi_imx->chipselect[config->cs];
|
||||
|
||||
reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
|
||||
MX27_CSPICTRL_DR_SHIFT;
|
||||
|
|
@ -286,19 +451,24 @@ static int mx27_config(struct spi_imx_data *spi_imx,
|
|||
reg |= MX27_CSPICTRL_POL;
|
||||
if (config->mode & SPI_CS_HIGH)
|
||||
reg |= MX27_CSPICTRL_SSPOL;
|
||||
if (config->cs < 0)
|
||||
reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
|
||||
if (cs < 0)
|
||||
reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
|
||||
|
||||
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mx27_rx_available(struct spi_imx_data *spi_imx)
|
||||
static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
|
||||
}
|
||||
|
||||
static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
writel(1, spi_imx->base + MXC_RESET);
|
||||
}
|
||||
|
||||
#define MX1_INTREG_RR (1 << 3)
|
||||
#define MX1_INTREG_TEEN (1 << 8)
|
||||
#define MX1_INTREG_RREN (1 << 11)
|
||||
|
|
@ -310,7 +480,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
|
|||
#define MX1_CSPICTRL_MASTER (1 << 10)
|
||||
#define MX1_CSPICTRL_DR_SHIFT 13
|
||||
|
||||
static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
||||
static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
|
||||
|
|
@ -322,7 +492,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
|
|||
writel(val, spi_imx->base + MXC_CSPIINT);
|
||||
}
|
||||
|
||||
static void mx1_trigger(struct spi_imx_data *spi_imx)
|
||||
static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
||||
|
|
@ -331,7 +501,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
|
|||
writel(reg, spi_imx->base + MXC_CSPICTRL);
|
||||
}
|
||||
|
||||
static int mx1_config(struct spi_imx_data *spi_imx,
|
||||
static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
|
||||
struct spi_imx_config *config)
|
||||
{
|
||||
unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
|
||||
|
|
@ -350,11 +520,73 @@ static int mx1_config(struct spi_imx_data *spi_imx,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int mx1_rx_available(struct spi_imx_data *spi_imx)
|
||||
static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
|
||||
}
|
||||
|
||||
static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
writel(1, spi_imx->base + MXC_RESET);
|
||||
}
|
||||
|
||||
/*
|
||||
* These version numbers are taken from the Freescale driver. Unfortunately it
|
||||
* doesn't support i.MX1, so this entry doesn't match the scheme. :-(
|
||||
*/
|
||||
static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
|
||||
#ifdef CONFIG_SPI_IMX_VER_IMX1
|
||||
[SPI_IMX_VER_IMX1] = {
|
||||
.intctrl = mx1_intctrl,
|
||||
.config = mx1_config,
|
||||
.trigger = mx1_trigger,
|
||||
.rx_available = mx1_rx_available,
|
||||
.reset = mx1_reset,
|
||||
.fifosize = 8,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_IMX_VER_0_0
|
||||
[SPI_IMX_VER_0_0] = {
|
||||
.intctrl = mx27_intctrl,
|
||||
.config = mx27_config,
|
||||
.trigger = mx27_trigger,
|
||||
.rx_available = mx27_rx_available,
|
||||
.reset = spi_imx0_0_reset,
|
||||
.fifosize = 8,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_IMX_VER_0_4
|
||||
[SPI_IMX_VER_0_4] = {
|
||||
.intctrl = mx31_intctrl,
|
||||
.config = spi_imx0_4_config,
|
||||
.trigger = mx31_trigger,
|
||||
.rx_available = mx31_rx_available,
|
||||
.reset = spi_imx0_4_reset,
|
||||
.fifosize = 8,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_IMX_VER_0_7
|
||||
[SPI_IMX_VER_0_7] = {
|
||||
.intctrl = mx31_intctrl,
|
||||
.config = spi_imx0_7_config,
|
||||
.trigger = mx31_trigger,
|
||||
.rx_available = mx31_rx_available,
|
||||
.reset = spi_imx0_4_reset,
|
||||
.fifosize = 8,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_SPI_IMX_VER_2_3
|
||||
[SPI_IMX_VER_2_3] = {
|
||||
.intctrl = spi_imx2_3_intctrl,
|
||||
.config = spi_imx2_3_config,
|
||||
.trigger = spi_imx2_3_trigger,
|
||||
.rx_available = spi_imx2_3_rx_available,
|
||||
.reset = spi_imx2_3_reset,
|
||||
.fifosize = 64,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static void spi_imx_chipselect(struct spi_device *spi, int is_active)
|
||||
{
|
||||
struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
|
||||
|
|
@ -370,21 +602,21 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
|
|||
|
||||
static void spi_imx_push(struct spi_imx_data *spi_imx)
|
||||
{
|
||||
while (spi_imx->txfifo < 8) {
|
||||
while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
|
||||
if (!spi_imx->count)
|
||||
break;
|
||||
spi_imx->tx(spi_imx);
|
||||
spi_imx->txfifo++;
|
||||
}
|
||||
|
||||
spi_imx->trigger(spi_imx);
|
||||
spi_imx->devtype_data.trigger(spi_imx);
|
||||
}
|
||||
|
||||
static irqreturn_t spi_imx_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_imx_data *spi_imx = dev_id;
|
||||
|
||||
while (spi_imx->rx_available(spi_imx)) {
|
||||
while (spi_imx->devtype_data.rx_available(spi_imx)) {
|
||||
spi_imx->rx(spi_imx);
|
||||
spi_imx->txfifo--;
|
||||
}
|
||||
|
|
@ -398,11 +630,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
|
|||
/* No data left to push, but still waiting for rx data,
|
||||
* enable receive data available interrupt.
|
||||
*/
|
||||
spi_imx->intctrl(spi_imx, MXC_INT_RR);
|
||||
spi_imx->devtype_data.intctrl(
|
||||
spi_imx, MXC_INT_RR);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
spi_imx->intctrl(spi_imx, 0);
|
||||
spi_imx->devtype_data.intctrl(spi_imx, 0);
|
||||
complete(&spi_imx->xfer_done);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -417,7 +650,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
|
|||
config.bpw = t ? t->bits_per_word : spi->bits_per_word;
|
||||
config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
|
||||
config.mode = spi->mode;
|
||||
config.cs = spi_imx->chipselect[spi->chip_select];
|
||||
config.cs = spi->chip_select;
|
||||
|
||||
if (!config.speed_hz)
|
||||
config.speed_hz = spi->max_speed_hz;
|
||||
|
|
@ -439,7 +672,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
|
|||
} else
|
||||
BUG();
|
||||
|
||||
spi_imx->config(spi_imx, &config);
|
||||
spi_imx->devtype_data.config(spi_imx, &config);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -458,7 +691,7 @@ static int spi_imx_transfer(struct spi_device *spi,
|
|||
|
||||
spi_imx_push(spi_imx);
|
||||
|
||||
spi_imx->intctrl(spi_imx, MXC_INT_TE);
|
||||
spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
|
||||
|
||||
wait_for_completion(&spi_imx->xfer_done);
|
||||
|
||||
|
|
@ -485,6 +718,39 @@ static void spi_imx_cleanup(struct spi_device *spi)
|
|||
{
|
||||
}
|
||||
|
||||
static struct platform_device_id spi_imx_devtype[] = {
|
||||
{
|
||||
.name = DRIVER_NAME,
|
||||
.driver_data = SPI_IMX_VER_AUTODETECT,
|
||||
}, {
|
||||
.name = "imx1-cspi",
|
||||
.driver_data = SPI_IMX_VER_IMX1,
|
||||
}, {
|
||||
.name = "imx21-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_0,
|
||||
}, {
|
||||
.name = "imx25-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_7,
|
||||
}, {
|
||||
.name = "imx27-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_0,
|
||||
}, {
|
||||
.name = "imx31-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_4,
|
||||
}, {
|
||||
.name = "imx35-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_7,
|
||||
}, {
|
||||
.name = "imx51-cspi",
|
||||
.driver_data = SPI_IMX_VER_0_7,
|
||||
}, {
|
||||
.name = "imx51-ecspi",
|
||||
.driver_data = SPI_IMX_VER_2_3,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int __devinit spi_imx_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_imx_master *mxc_platform_info;
|
||||
|
|
@ -536,6 +802,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|||
|
||||
init_completion(&spi_imx->xfer_done);
|
||||
|
||||
if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
|
||||
if (cpu_is_mx25() || cpu_is_mx35())
|
||||
spi_imx->devtype_data =
|
||||
spi_imx_devtype_data[SPI_IMX_VER_0_7];
|
||||
else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
|
||||
spi_imx->devtype_data =
|
||||
spi_imx_devtype_data[SPI_IMX_VER_0_4];
|
||||
else if (cpu_is_mx27() || cpu_is_mx21())
|
||||
spi_imx->devtype_data =
|
||||
spi_imx_devtype_data[SPI_IMX_VER_0_0];
|
||||
else if (cpu_is_mx1())
|
||||
spi_imx->devtype_data =
|
||||
spi_imx_devtype_data[SPI_IMX_VER_IMX1];
|
||||
else
|
||||
BUG();
|
||||
} else
|
||||
spi_imx->devtype_data =
|
||||
spi_imx_devtype_data[pdev->id_entry->driver_data];
|
||||
|
||||
if (!spi_imx->devtype_data.intctrl) {
|
||||
dev_err(&pdev->dev, "no support for this device compiled in\n");
|
||||
ret = -ENODEV;
|
||||
goto out_gpio_free;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "can't get platform resource\n");
|
||||
|
|
@ -567,24 +858,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|||
goto out_iounmap;
|
||||
}
|
||||
|
||||
if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
|
||||
spi_imx->intctrl = mx31_intctrl;
|
||||
spi_imx->config = mx31_config;
|
||||
spi_imx->trigger = mx31_trigger;
|
||||
spi_imx->rx_available = mx31_rx_available;
|
||||
} else if (cpu_is_mx27() || cpu_is_mx21()) {
|
||||
spi_imx->intctrl = mx27_intctrl;
|
||||
spi_imx->config = mx27_config;
|
||||
spi_imx->trigger = mx27_trigger;
|
||||
spi_imx->rx_available = mx27_rx_available;
|
||||
} else if (cpu_is_mx1()) {
|
||||
spi_imx->intctrl = mx1_intctrl;
|
||||
spi_imx->config = mx1_config;
|
||||
spi_imx->trigger = mx1_trigger;
|
||||
spi_imx->rx_available = mx1_rx_available;
|
||||
} else
|
||||
BUG();
|
||||
|
||||
spi_imx->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(spi_imx->clk)) {
|
||||
dev_err(&pdev->dev, "unable to get clock\n");
|
||||
|
|
@ -595,15 +868,9 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
|
|||
clk_enable(spi_imx->clk);
|
||||
spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
|
||||
|
||||
if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
|
||||
writel(1, spi_imx->base + MXC_RESET);
|
||||
spi_imx->devtype_data.reset(spi_imx);
|
||||
|
||||
/* drain receive buffer */
|
||||
if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
|
||||
while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
|
||||
readl(spi_imx->base + MXC_CSPIRXDATA);
|
||||
|
||||
spi_imx->intctrl(spi_imx, 0);
|
||||
spi_imx->devtype_data.intctrl(spi_imx, 0);
|
||||
|
||||
ret = spi_bitbang_start(&spi_imx->bitbang);
|
||||
if (ret) {
|
||||
|
|
@ -668,6 +935,7 @@ static struct platform_driver spi_imx_driver = {
|
|||
.name = DRIVER_NAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.id_table = spi_imx_devtype,
|
||||
.probe = spi_imx_probe,
|
||||
.remove = __devexit_p(spi_imx_remove),
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in a new issue