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drm/amd/display: Add missing MI masks

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This will fix the memory Input programing with MST tiled display.
This Fix should fix connectivity problems with MST tiled Display

Signed-off-by: Leon Elazar <leon.elazar@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Leon Elazar 2017-01-17 16:16:04 -05:00 • committed by Alex Deucher
commit b565ff86aa
1 changed files with 2 additions and 0 deletions
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drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
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@ -92,6 +92,8 @@ struct dce_mem_input_registers {
.field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
#define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\
SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\
SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\