diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 906f11685d96..93709ab8e29b 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -56,6 +56,9 @@ SoCs: - SHIMA compatible = "qcom,shima" +- YUPIK + compatible = "qcom,yupik" + - LITO compatible = "qcom,lito" @@ -206,6 +209,7 @@ compatible = "qcom,shima-rumi" compatible = "qcom,shima-idp" compatible = "qcom,shima-atp" compatible = "qcom,shima-qrd" +compatible = "qcom,yupik-rumi" compatible = "qcom,lito-rumi" compatible = "qcom,lito-mtp" compatible = "qcom,lito-cdp" diff --git a/bindings/pinctrl/qcom,yupik-pinctrl.txt b/bindings/pinctrl/qcom,yupik-pinctrl.txt new file mode 100644 index 000000000000..819fd937ecd8 --- /dev/null +++ b/bindings/pinctrl/qcom,yupik-pinctrl.txt @@ -0,0 +1,191 @@ +Qualcomm Technologies, Inc. YUPIK TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +YUPIK platform. + +- compatible: + Usage: required + Value type: + Definition: must be "qcom,yupik-pinctrl" + +- reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + +- wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio174 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + +- function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + +- bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@f000000 { + compatible = "qcom,yupik-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 431e168ae8a3..1a1c6f058bd8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -122,6 +122,15 @@ dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idps-digital-mics.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_YUPIK) += \ + yupik-rumi-overlay.dtbo + +yupik-rumi-overlay.dtbo-base := yupik.dtb +else +dtb-$(CONFIG_ARCH_YUPIK) += yupik-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SM8150) += \ sm8150-cdp-overlay.dtbo \ diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi new file mode 100644 index 000000000000..f878cb95d247 --- /dev/null +++ b/qcom/yupik-pinctrl.dtsi @@ -0,0 +1,11 @@ +&soc { + tlmm: pinctrl@f000000 { + compatible = "qcom,yupik-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; diff --git a/qcom/yupik-rumi-overlay.dts b/qcom/yupik-rumi-overlay.dts new file mode 100644 index 000000000000..45ef5d896d3f --- /dev/null +++ b/qcom/yupik-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,msm-id = <475 0x10000>; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dts b/qcom/yupik-rumi.dts new file mode 100644 index 000000000000..2085858de82d --- /dev/null +++ b/qcom/yupik-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00000100; + +#include "yupik.dtsi" +#include "yupik-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik RUMI"; + compatible = "qcom,yupik-rumi", "qcom,yupik", "qcom,rumi"; + qcom,board-id = <0x1000f 0>; +}; diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi new file mode 100644 index 000000000000..0987448b8be5 --- /dev/null +++ b/qcom/yupik-rumi.dtsi @@ -0,0 +1,13 @@ +&soc { + timer { + clock-frequency = <5000000>; + }; + + timer@17c20000 { + clock-frequency = <5000000>; + }; + + wdog: qcom,wdt@17c10000 { + status = "disabled"; + }; +}; diff --git a/qcom/yupik-stub-regulator.dtsi b/qcom/yupik-stub-regulator.dtsi new file mode 100644 index 000000000000..fc699ff09167 --- /dev/null +++ b/qcom/yupik-stub-regulator.dtsi @@ -0,0 +1,471 @@ +#include + +/ { + VDD_GFX_LEVEL: + S7C_LEVEL: + pm8350c_s7_level: regulator-pm8350c-s7-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s7_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S1B: + pm74xx_s1: regulator-pm74xx-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2040000>; + }; + + S2B: + pm74xx_s2: regulator-pm74xx-s2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <640000>; + regulator-max-microvolt = <1050000>; + }; + + S7B: + pm74xx_s7: regulator-pm74xx-s7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <535000>; + regulator-max-microvolt = <1120000>; + }; + + S8B: + pm74xx_s8: regulator-pm74xx-s8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_s8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1500000>; + }; + + L1B: + pm74xx_l1: regulator-pm74xx-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <925000>; + }; + + L2B: + pm74xx_l2: regulator-pm74xx-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + VDD_IO_EBI_LEVEL: + L3B_LEVEL: + pm74xx_l3_level: regulator-pm74xx-l3-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l3_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_LPI_MX_LEVEL: + L4B_LEVEL: + pm74xx_l4_level: regulator-pm74xx-l4-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l4_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_LPI_CX_LEVEL: + L5B_LEVEL: + pm74xx_l5_level: regulator-pm74xx-l5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L6B: + pm74xx_l6: regulator-pm74xx-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L7B: + pm74xx_l7: regulator-pm74xx-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3544000>; + }; + + L8B: + pm74xx_l8: regulator-pm74xx-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <870000>; + regulator-max-microvolt = <970000>; + }; + + L9B: + pm74xx_l9: regulator-pm74xx-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L10B: + pm74xx_l10: regulator-pm74xx-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + L11B: + pm74xx_l11: regulator-pm74xx-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L12B: + pm74xx_l12: regulator-pm74xx-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + L13B: + pm74xx_l13: regulator-pm74xx-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <530000>; + regulator-max-microvolt = <824000>; + }; + + L14B: + pm74xx_l14: regulator-pm74xx-l14 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l14"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + L15B: + pm74xx_l15: regulator-pm74xx-l15 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l15"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + L16B: + pm74xx_l16: regulator-pm74xx-l16 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l16"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1139000>; + regulator-max-microvolt = <1236000>; + }; + + L17B: + pm74xx_l17: regulator-pm74xx-l17 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l17"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + L18B: + pm74xx_l18: regulator-pm74xx-l18 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l18"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L19B: + pm74xx_l19: regulator-pm74xx-l19 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm74xx_l19"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + S1C: + pm8350c_s1: regulator-pm8350c-s1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2160000>; + regulator-max-microvolt = <2200000>; + }; + + VDD_MODEM_LEVEL: + S5C_LEVEL: + pm8350c_s5_level: regulator-pm8350c-s5-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s5_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL: + S2C_LEVEL: + pm8350c_s2_level: regulator-pm8350c-s2-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s2_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_CX_LEVEL_AO: + S2C_LEVEL_AO: + pm8350c_s2_level_ao: regulator-pm8350c-s2-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s2_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + S9C: + pm8350c_s9: regulator-pm8350c-s9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + + VDD_MX_LEVEL: + S10C_LEVEL: + pm8350c_s10_level: regulator-pm8350c-s10-level { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s10_level"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + VDD_MX_LEVEL_AO: + S10C_LEVEL_AO: + pm8350c_s10_level_ao: regulator-pm8350c-s10-level-ao { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_s10_level_ao"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = ; + regulator-max-microvolt = ; + }; + + L1C: + pm8350c_l1: regulator-pm8350c-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L2C: + pm8350c_l2: regulator-pm8350c-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L3C: + pm8350c_l3: regulator-pm8350c-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3544000>; + }; + + L4C: + pm8350c_l4: regulator-pm8350c-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L5C: + pm8350c_l5: regulator-pm8350c-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + }; + + L6C: + pm8350c_l6: regulator-pm8350c-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + L7C: + pm8350c_l7: regulator-pm8350c-l7 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l7"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + L8C: + pm8350c_l8: regulator-pm8350c-l8 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l8"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + L9C: + pm8350c_l9: regulator-pm8350c-l9 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l9"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L10C: + pm8350c_l10: regulator-pm8350c-l10 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l10"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + L11C: + pm8350c_l11: regulator-pm8350c-l11 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l11"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + L12C: + pm8350c_l12: regulator-pm8350c-l12 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l12"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + L13C: + pm8350c_l13: regulator-pm8350c-l13 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_l13"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + + L1D: + pm8350b_l1: regulator-pm8350b-l1 { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350b_l1"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + BOB: + pm8350c_bob: regulator-pm8350c-bob { + compatible = "qcom,stub-regulator"; + regulator-name = "pm8350c_bob"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3960000>; + }; + + L2E: + pmr735a_l2: regulator-pmr735a-l2 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l2"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1260000>; + }; + + L3E: + pmr735a_l3: regulator-pmr735a-l3 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l3"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <765000>; + regulator-max-microvolt = <1020000>; + }; + + L4E: + pmr735a_l4: regulator-pmr735a-l4 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l4"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <1615000>; + regulator-max-microvolt = <1890000>; + }; + + L5E: + pmr735a_l5: regulator-pmr735a-l5 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l5"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <760000>; + regulator-max-microvolt = <840000>; + }; + + L6E: + pmr735a_l6: regulator-pmr735a-l6 { + compatible = "qcom,stub-regulator"; + regulator-name = "pmr735a_l6"; + qcom,hpm-min-load = <10000>; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <880000>; + }; +}; diff --git a/qcom/yupik.dts b/qcom/yupik.dts new file mode 100644 index 000000000000..07edde8dc0a5 --- /dev/null +++ b/qcom/yupik.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "yupik.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Yupik SoC"; + compatible = "qcom,yupik"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi new file mode 100644 index 000000000000..74b1ab864224 --- /dev/null +++ b/qcom/yupik.dtsi @@ -0,0 +1,269 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Yupik"; + compatible = "qcom,yupik"; + qcom,msm-id = <475 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; + + chosen { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17c10000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17c10000 0x1000>; + reg-names = "wdt-base"; + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17c20000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c20000 0x1000>; + clock-frequency = <19200000>; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x17c23000 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x17c25000 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x17c27000 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x17c29000 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x17c2b000 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x17c2d000 0x1000>; + status = "disabled"; + }; + }; +}; + +#include "yupik-pinctrl.dtsi" +#include "yupik-stub-regulator.dtsi"