diff --git a/drivers/clk/qcom/gcc-shima.c b/drivers/clk/qcom/gcc-shima.c index 742b3b53a4d5..a8601b193fc7 100644 --- a/drivers/clk/qcom/gcc-shima.c +++ b/drivers/clk/qcom/gcc-shima.c @@ -1833,6 +1833,19 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { }, }; +static struct clk_branch gcc_gpu_iref_en = { + .halt_reg = 0x8c014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_iref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_gpu_memnoc_gfx_clk = { .halt_reg = 0x7100c, .halt_check = BRANCH_HALT_VOTED, @@ -2797,6 +2810,19 @@ static struct clk_branch gcc_titan_rt_throttle_core_clk = { }, }; +static struct clk_branch gcc_ufs_1_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_1_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_ufs_phy_ahb_clk = { .halt_reg = 0x77018, .halt_check = BRANCH_HALT_VOTED, @@ -3258,6 +3284,7 @@ static struct clk_regmap *gcc_shima_clocks[] = { [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_GPU_IREF_EN] = &gcc_gpu_iref_en.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_PCIE0_PHY_RCHNG_CLK] = &gcc_pcie0_phy_rchng_clk.clkr, @@ -3346,6 +3373,7 @@ static struct clk_regmap *gcc_shima_clocks[] = { [GCC_TITAN_NRT_THROTTLE_CORE_CLK] = &gcc_titan_nrt_throttle_core_clk.clkr, [GCC_TITAN_RT_THROTTLE_CORE_CLK] = &gcc_titan_rt_throttle_core_clk.clkr, + [GCC_UFS_1_CLKREF_EN] = &gcc_ufs_1_clkref_en.clkr, [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, diff --git a/include/dt-bindings/clock/qcom,gcc-shima.h b/include/dt-bindings/clock/qcom,gcc-shima.h index e3828d2eb282..ef27c74a1b90 100644 --- a/include/dt-bindings/clock/qcom,gcc-shima.h +++ b/include/dt-bindings/clock/qcom,gcc-shima.h @@ -40,130 +40,132 @@ #define GCC_GPU_CFG_AHB_CLK 30 #define GCC_GPU_GPLL0_CLK_SRC 31 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 -#define GCC_GPU_MEMNOC_GFX_CLK 33 -#define GCC_GPU_SNOC_DVM_GFX_CLK 34 -#define GCC_PCIE0_PHY_RCHNG_CLK 35 -#define GCC_PCIE1_PHY_RCHNG_CLK 36 -#define GCC_PCIE_0_AUX_CLK 37 -#define GCC_PCIE_0_AUX_CLK_SRC 38 -#define GCC_PCIE_0_CFG_AHB_CLK 39 -#define GCC_PCIE_0_MSTR_AXI_CLK 40 -#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 41 -#define GCC_PCIE_0_PIPE_CLK 42 -#define GCC_PCIE_0_PIPE_CLK_SRC 43 -#define GCC_PCIE_0_SLV_AXI_CLK 44 -#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 -#define GCC_PCIE_1_AUX_CLK 46 -#define GCC_PCIE_1_AUX_CLK_SRC 47 -#define GCC_PCIE_1_CFG_AHB_CLK 48 -#define GCC_PCIE_1_MSTR_AXI_CLK 49 -#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 50 -#define GCC_PCIE_1_PIPE_CLK 51 -#define GCC_PCIE_1_PIPE_CLK_SRC 52 -#define GCC_PCIE_1_SLV_AXI_CLK 53 -#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 54 -#define GCC_PCIE_THROTTLE_CORE_CLK 55 -#define GCC_PDM2_CLK 56 -#define GCC_PDM2_CLK_SRC 57 -#define GCC_PDM_AHB_CLK 58 -#define GCC_PDM_XO4_CLK 59 -#define GCC_QMIP_CAMERA_NRT_AHB_CLK 60 -#define GCC_QMIP_CAMERA_RT_AHB_CLK 61 -#define GCC_QMIP_DISP_AHB_CLK 62 -#define GCC_QMIP_VIDEO_CVP_AHB_CLK 63 -#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 64 -#define GCC_QUPV3_WRAP0_CORE_2X_CLK 65 -#define GCC_QUPV3_WRAP0_CORE_CLK 66 -#define GCC_QUPV3_WRAP0_S0_CLK 67 -#define GCC_QUPV3_WRAP0_S0_CLK_SRC 68 -#define GCC_QUPV3_WRAP0_S1_CLK 69 -#define GCC_QUPV3_WRAP0_S1_CLK_SRC 70 -#define GCC_QUPV3_WRAP0_S2_CLK 71 -#define GCC_QUPV3_WRAP0_S2_CLK_SRC 72 -#define GCC_QUPV3_WRAP0_S3_CLK 73 -#define GCC_QUPV3_WRAP0_S3_CLK_SRC 74 -#define GCC_QUPV3_WRAP0_S4_CLK 75 -#define GCC_QUPV3_WRAP0_S4_CLK_SRC 76 -#define GCC_QUPV3_WRAP0_S5_CLK 77 -#define GCC_QUPV3_WRAP0_S5_CLK_SRC 78 -#define GCC_QUPV3_WRAP0_S6_CLK 79 -#define GCC_QUPV3_WRAP0_S6_CLK_SRC 80 -#define GCC_QUPV3_WRAP0_S7_CLK 81 -#define GCC_QUPV3_WRAP0_S7_CLK_SRC 82 -#define GCC_QUPV3_WRAP1_CORE_2X_CLK 83 -#define GCC_QUPV3_WRAP1_CORE_CLK 84 -#define GCC_QUPV3_WRAP1_S0_CLK 85 -#define GCC_QUPV3_WRAP1_S0_CLK_SRC 86 -#define GCC_QUPV3_WRAP1_S1_CLK 87 -#define GCC_QUPV3_WRAP1_S1_CLK_SRC 88 -#define GCC_QUPV3_WRAP1_S2_CLK 89 -#define GCC_QUPV3_WRAP1_S2_CLK_SRC 90 -#define GCC_QUPV3_WRAP1_S3_CLK 91 -#define GCC_QUPV3_WRAP1_S3_CLK_SRC 92 -#define GCC_QUPV3_WRAP1_S4_CLK 93 -#define GCC_QUPV3_WRAP1_S4_CLK_SRC 94 -#define GCC_QUPV3_WRAP1_S5_CLK 95 -#define GCC_QUPV3_WRAP1_S5_CLK_SRC 96 -#define GCC_QUPV3_WRAP1_S6_CLK 97 -#define GCC_QUPV3_WRAP1_S6_CLK_SRC 98 -#define GCC_QUPV3_WRAP1_S7_CLK 99 -#define GCC_QUPV3_WRAP1_S7_CLK_SRC 100 -#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101 -#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102 -#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103 -#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104 -#define GCC_SDCC1_AHB_CLK 105 -#define GCC_SDCC1_APPS_CLK 106 -#define GCC_SDCC1_APPS_CLK_SRC 107 -#define GCC_SDCC1_ICE_CORE_CLK 108 -#define GCC_SDCC1_ICE_CORE_CLK_SRC 109 -#define GCC_SDCC2_AHB_CLK 110 -#define GCC_SDCC2_APPS_CLK 111 -#define GCC_SDCC2_APPS_CLK_SRC 112 -#define GCC_SDCC4_AHB_CLK 113 -#define GCC_SDCC4_APPS_CLK 114 -#define GCC_SDCC4_APPS_CLK_SRC 115 -#define GCC_SYS_NOC_CPUSS_AHB_CLK 116 -#define GCC_THROTTLE_PCIE_AHB_CLK 117 -#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 118 -#define GCC_TITAN_RT_THROTTLE_CORE_CLK 119 -#define GCC_UFS_PHY_AHB_CLK 120 -#define GCC_UFS_PHY_AXI_CLK 121 -#define GCC_UFS_PHY_AXI_CLK_SRC 122 -#define GCC_UFS_PHY_ICE_CORE_CLK 123 -#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 124 -#define GCC_UFS_PHY_PHY_AUX_CLK 125 -#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 126 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 127 -#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 128 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 129 -#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 130 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 131 -#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 132 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK 133 -#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 134 -#define GCC_USB30_PRIM_MASTER_CLK 135 -#define GCC_USB30_PRIM_MASTER_CLK_SRC 136 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK 137 -#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 138 -#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 139 -#define GCC_USB30_PRIM_SLEEP_CLK 140 -#define GCC_USB3_PRIM_PHY_AUX_CLK 141 -#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 142 -#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 143 -#define GCC_USB3_PRIM_PHY_PIPE_CLK 144 -#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 145 -#define GCC_VIDEO_AHB_CLK 146 -#define GCC_VIDEO_AXI0_CLK 147 -#define GCC_VIDEO_AXI1_CLK 148 -#define GCC_VIDEO_CVP_THROTTLE_CORE_CLK 149 -#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 150 -#define GCC_VIDEO_XO_CLK 151 -#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 152 -#define GCC_UFS_PHY_AXI_HW_CTL_CLK 153 -#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 154 -#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 155 -#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 156 +#define GCC_GPU_IREF_EN 33 +#define GCC_GPU_MEMNOC_GFX_CLK 34 +#define GCC_GPU_SNOC_DVM_GFX_CLK 35 +#define GCC_PCIE0_PHY_RCHNG_CLK 36 +#define GCC_PCIE1_PHY_RCHNG_CLK 37 +#define GCC_PCIE_0_AUX_CLK 38 +#define GCC_PCIE_0_AUX_CLK_SRC 39 +#define GCC_PCIE_0_CFG_AHB_CLK 40 +#define GCC_PCIE_0_MSTR_AXI_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_PIPE_CLK_SRC 44 +#define GCC_PCIE_0_SLV_AXI_CLK 45 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 46 +#define GCC_PCIE_1_AUX_CLK 47 +#define GCC_PCIE_1_AUX_CLK_SRC 48 +#define GCC_PCIE_1_CFG_AHB_CLK 49 +#define GCC_PCIE_1_MSTR_AXI_CLK 50 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 51 +#define GCC_PCIE_1_PIPE_CLK 52 +#define GCC_PCIE_1_PIPE_CLK_SRC 53 +#define GCC_PCIE_1_SLV_AXI_CLK 54 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 55 +#define GCC_PCIE_THROTTLE_CORE_CLK 56 +#define GCC_PDM2_CLK 57 +#define GCC_PDM2_CLK_SRC 58 +#define GCC_PDM_AHB_CLK 59 +#define GCC_PDM_XO4_CLK 60 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 61 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 62 +#define GCC_QMIP_DISP_AHB_CLK 63 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 64 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 65 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 66 +#define GCC_QUPV3_WRAP0_CORE_CLK 67 +#define GCC_QUPV3_WRAP0_S0_CLK 68 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S1_CLK 70 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 +#define GCC_QUPV3_WRAP0_S2_CLK 72 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 +#define GCC_QUPV3_WRAP0_S3_CLK 74 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 +#define GCC_QUPV3_WRAP0_S4_CLK 76 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 +#define GCC_QUPV3_WRAP0_S5_CLK 78 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 +#define GCC_QUPV3_WRAP0_S6_CLK 80 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 +#define GCC_QUPV3_WRAP0_S7_CLK 82 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 84 +#define GCC_QUPV3_WRAP1_CORE_CLK 85 +#define GCC_QUPV3_WRAP1_S0_CLK 86 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S1_CLK 88 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 89 +#define GCC_QUPV3_WRAP1_S2_CLK 90 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 91 +#define GCC_QUPV3_WRAP1_S3_CLK 92 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 93 +#define GCC_QUPV3_WRAP1_S4_CLK 94 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 95 +#define GCC_QUPV3_WRAP1_S5_CLK 96 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 97 +#define GCC_QUPV3_WRAP1_S6_CLK 98 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 99 +#define GCC_QUPV3_WRAP1_S7_CLK 100 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 101 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 102 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 103 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 104 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 105 +#define GCC_SDCC1_AHB_CLK 106 +#define GCC_SDCC1_APPS_CLK 107 +#define GCC_SDCC1_APPS_CLK_SRC 108 +#define GCC_SDCC1_ICE_CORE_CLK 109 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 110 +#define GCC_SDCC2_AHB_CLK 111 +#define GCC_SDCC2_APPS_CLK 112 +#define GCC_SDCC2_APPS_CLK_SRC 113 +#define GCC_SDCC4_AHB_CLK 114 +#define GCC_SDCC4_APPS_CLK 115 +#define GCC_SDCC4_APPS_CLK_SRC 116 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 117 +#define GCC_THROTTLE_PCIE_AHB_CLK 118 +#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 119 +#define GCC_TITAN_RT_THROTTLE_CORE_CLK 120 +#define GCC_UFS_1_CLKREF_EN 121 +#define GCC_UFS_PHY_AHB_CLK 122 +#define GCC_UFS_PHY_AXI_CLK 123 +#define GCC_UFS_PHY_AXI_CLK_SRC 124 +#define GCC_UFS_PHY_ICE_CORE_CLK 125 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 126 +#define GCC_UFS_PHY_PHY_AUX_CLK 127 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 128 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 129 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 130 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 131 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 132 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 134 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 135 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 136 +#define GCC_USB30_PRIM_MASTER_CLK 137 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 138 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 139 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 140 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 141 +#define GCC_USB30_PRIM_SLEEP_CLK 142 +#define GCC_USB3_PRIM_PHY_AUX_CLK 143 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 144 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 145 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 146 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 147 +#define GCC_VIDEO_AHB_CLK 148 +#define GCC_VIDEO_AXI0_CLK 149 +#define GCC_VIDEO_AXI1_CLK 150 +#define GCC_VIDEO_CVP_THROTTLE_CORE_CLK 151 +#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 152 +#define GCC_VIDEO_XO_CLK 153 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 154 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 155 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 156 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 157 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 158 /* GCC resets */ #define GCC_PCIE_0_BCR 0