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ARM: dts: msm: add trusted vm dtsi files for Lahaina target

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Add trusted VM device tree files for Lahaina. These files
inherit common Lahaina target bindings and overrides with
needed bindings with VM specific values.

Change-Id: Icb3090d1dfa6afe7eb993064e4493140708b658e
This commit is contained in:
Jeykumar Sankaran 2020-06-20 00:15:04 -07:00
commit b765705d9b
2 changed files with 101 additions and 0 deletions
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33
display/trustedvm-lahaina-sde-display.dtsi Normal file
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#include "lahaina-sde-display-common.dtsi"
&sde_dsi {
clocks = <&clock_cpucc BYTECLK_MUX_0_CLK>,
<&clock_cpucc PCLK_MUX_0_CLK>,
<&clock_cpucc CPHY_BYTECLK_SRC_0_CLK>,
<&clock_cpucc CPHY_PCLK_SRC_0_CLK>,
<&clock_cpucc BYTECLK_SRC_0_CLK>,
<&clock_cpucc PCLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_BYTECLK_SRC_0_CLK>,
<&clock_cpucc SHADOW_PCLK_SRC_0_CLK>,
<&clock_cpucc BYTECLK_MUX_1_CLK>,
<&clock_cpucc PCLK_MUX_1_CLK>,
<&clock_cpucc CPHY_BYTECLK_SRC_1_CLK>,
<&clock_cpucc CPHY_PCLK_SRC_1_CLK>,
<&clock_cpucc BYTECLK_SRC_1_CLK>,
<&clock_cpucc PCLK_SRC_1_CLK>,
<&clock_cpucc SHADOW_BYTECLK_SRC_1_CLK>,
<&clock_cpucc SHADOW_PCLK_SRC_1_CLK>;
clock-names = "mux_byte_clk0", "mux_pixel_clk0",
"cphy_byte_clk0", "cphy_pixel_clk0",
"src_byte_clk0", "src_pixel_clk0",
"shadow_byte_clk0", "shadow_pixel_clk0",
"mux_byte_clk1", "mux_pixel_clk1",
"cphy_byte_clk1", "cphy_pixel_clk1",
"src_byte_clk1", "src_pixel_clk1",
"shadow_byte_clk1", "shadow_pixel_clk1";
qcom,panel-te-source = <0>;
};
&mdss_mdp {
connectors = <&sde_dsi>;
};

68
display/trustedvm-lahaina-sde.dtsi Normal file
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#include "lahaina-sde-common.dtsi"
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
&soc {
/* dummy display clock provider */
clock_cpucc: qcom,cpucc {
compatible = "qcom,dummycc";
clock-output-names = "cpucc_clocks";
#clock-cells = <1>;
};
};
&mdss_mdp {
reg = <0x0ae00000 0x84000>,
<0x0aeb0000 0x2008>,
<0x0aeac000 0x800>,
<0x0ae8f000 0x02c>;
reg-names = "mdp_phys",
"vbif_phys",
"regdma_phys",
"sid_phys";
qcom,sde-hw-version =<0x70000000>;
clocks =
<&clock_cpucc GCC_DISP_AHB_CLK>,
<&clock_cpucc GCC_DISP_HF_AXI_CLK>,
<&clock_cpucc GCC_DISP_SF_AXI_CLK>,
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>,
<&clock_cpucc DISP_CC_MDSS_ROT_CLK>;
clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
"iface_clk", "core_clk", "vsync_clk",
"lut_clk", "rot_clk";
};
&mdss_dsi0 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi1 {
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE1_CLK>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK>,
<&clock_cpucc DISP_CC_MDSS_PCLK1_CLK_SRC>,
<&clock_cpucc DISP_CC_MDSS_ESC1_CLK>;
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
"pixel_clk", "pixel_clk_rcg", "esc_clk";
};
&mdss_dsi_phy0 {
qcom,dsi-pll-in-trusted-vm;
};
&mdss_dsi_phy1 {
qcom,dsi-pll-in-trusted-vm;
};