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ARM: dts: msm: Update DISPCC and debugcc clock nodes for YUPIK

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Update the display clock controller node to real from dummmy and
add debug clock controller node for YUPIK.

Change-Id: I2211792d6c26f7f234cc507129438e52106971f6
This commit is contained in:
Jagadeesh Kona 2020-12-29 13:07:17 +05:30
commit b77c2fed79
2 changed files with 40 additions and 2 deletions
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9
qcom/yupik-rumi.dtsi
View file

@ -191,3 +191,12 @@
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
status = "disabled";
};
&dispcc {
clocks = <&bi_tcxo>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_AHB_CLK>;
};
&debugcc {
clocks = <&bi_tcxo>;
};

33
qcom/yupik.dtsi
View file

@ -951,8 +951,13 @@
};
dispcc: clock-controller@af00000 {
compatible = "qcom,dummycc";
clock-output-names = "dispcc_clocks";
compatible = "qcom,yupik-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk","cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
@ -983,6 +988,30 @@
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,yupik-debugcc";
qcom,gcc = <&gcc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,videocc = <&videocc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,