From b80d5e6948d270d1c570c1bf6d7313ea9cdf1768 Mon Sep 17 00:00:00 2001 From: Victor Zaharchuk Date: Sun, 28 Feb 2021 21:28:55 +0200 Subject: [PATCH] ARM: dts: msm: Add UFS ICE HW Node for SA8195 and SM8150 Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150. Change-Id: I0cf94e9d87cf3785ecf2d99c273694f8c44e2645 --- qcom/sdmshrike.dtsi | 16 ++++++++++++++++ qcom/sm8150.dtsi | 20 ++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 233b0219f67e..6333ee3f9bdf 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1098,6 +1098,22 @@ clock-frequency = <32768>; }; + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + disp_rsc: rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6ab0bcce7f5c..3e8cba84ed8b 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1501,6 +1501,26 @@ reg = <0x17c0000c 0x4>; }; + + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + apss_shared: mailbox@17c00000 { compatible = "qcom,sm8150-apss-shared"; reg = <0x17c00000 0x1000>;