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wsa: soundwire: Add support for 4p8MHz DAC rate

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Add support to use 4p8MHz DAC rate for receiver
over WSA.

Change-Id: Ia0811670326be8131687fbdff70464da063902b2
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam 2021-03-01 19:58:10 +05:30
commit b82a120fb9
4 changed files with 55 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

4
asoc/codecs/bolero/wsa-macro.c
View file

@ -1716,6 +1716,8 @@ static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x00);
}
break;
case SND_SOC_DAPM_POST_PMD:
@ -1731,6 +1733,8 @@ static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
dev_dbg(wsa_priv->dev, "%s: Reset RX0 Volume to 0 dB\n",
__func__);
}
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x08);
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
snd_soc_component_update_bits(component,

24
asoc/codecs/wsa883x/wsa883x.c
View file

@ -1000,6 +1000,8 @@ static int wsa883x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
&port_id[num_port], &num_ch[num_port],
&ch_mask[num_port], &ch_rate[num_port],
&port_type[num_port]);
if (wsa883x->dev_mode == RECEIVER)
ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
++num_port;
if (wsa883x->comp_enable) {
@ -1073,12 +1075,13 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
swr_slvdev_datapath_control(wsa883x->swr_slave,
wsa883x->swr_slave->dev_num,
true);
/* Added delay as per HW sequence */
usleep_range(250, 300);
if (wsa883x->dev_mode == RECEIVER) {
snd_soc_component_update_bits(component,
WSA883X_CDC_PATH_MODE,
0x02, 0x02);
snd_soc_component_update_bits(component,
WSA883X_SPKR_PWM_CLK_CTL,
0x08, 0x08);
snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_0,
0xF0, 0x00);
@ -1086,6 +1089,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
WSA883X_DRE_CTL_0,
0x07, 0x04);
} else if (wsa883x->dev_mode == SPEAKER) {
snd_soc_component_update_bits(component,
WSA883X_CDC_PATH_MODE,
0x02, 0x00);
snd_soc_component_update_bits(component,
WSA883X_SPKR_PWM_CLK_CTL,
0x08, 0x00);
snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_0,
0xF0, 0x90);
@ -1098,6 +1107,11 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
WSA883X_DRE_CTL_0,
0x07, 0x02);
}
swr_slvdev_datapath_control(wsa883x->swr_slave,
wsa883x->swr_slave->dev_num,
true);
/* Added delay as per HW sequence */
usleep_range(250, 300);
snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_1,
0x01, 0x01);

14
asoc/lahaina-port-config.h
View file

@ -26,6 +26,17 @@ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
};
static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 2, 3, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{63, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{3, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
};
static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00},
@ -110,6 +121,7 @@ static struct swr_mstr_port_map sm_port_map[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
};
static struct swr_mstr_port_map sm_port_map_shima[] = {
@ -120,6 +132,7 @@ static struct swr_mstr_port_map sm_port_map_shima[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
};
static struct swr_mstr_port_map sm_port_map_wcd937x[] = {
@ -130,6 +143,7 @@ static struct swr_mstr_port_map sm_port_map_wcd937x[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
};
#endif /* _LAHAINA_PORT_CONFIG */

20
soc/swr-mstr-ctrl.c
View file

@ -41,6 +41,8 @@
#define SWRM_DSD_PARAMS_PORT 4
#define SWRM_SPK_DAC_PORT_RECEIVER 0
#define SWR_BROADCAST_CMD_ID 0x0F
#define SWR_DEV_ID_MASK 0xFFFFFFFFFFFF
#define SWR_REG_VAL_PACK(data, dev, id, reg) \
@ -771,6 +773,12 @@ static int swrm_get_port_config(struct swr_mstr_ctrl *swrm)
else if (swrm->bus_clk == SWR_CLK_RATE_0P6MHZ)
usecase = 2;
if ((swrm->master_id == MASTER_ID_WSA) &&
swrm->mport_cfg[SWRM_SPK_DAC_PORT_RECEIVER].port_en &&
swrm->mport_cfg[SWRM_SPK_DAC_PORT_RECEIVER].ch_rate ==
SWR_CLK_RATE_4P8MHZ)
usecase = 1;
params = swrm->port_param[usecase];
copy_port_tables(swrm, params);
@ -1495,8 +1503,7 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
port_req->dev_num, 0x00,
SWRS_DP_BLOCK_CONTROL_1(slv_id));
}
if (port_req->blk_pack_mode != SWR_INVALID_PARAM
&& swrm->master_id != MASTER_ID_WSA) {
if (port_req->blk_pack_mode != SWR_INVALID_PARAM) {
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] =
SWR_REG_VAL_PACK(
@ -1827,6 +1834,15 @@ static int swrm_connect_port(struct swr_master *master,
swrm->dynamic_port_map_supported) {
mport->ch_rate += portinfo->ch_rate[i];
swrm_update_bus_clk(swrm);
} else {
/*
* Fallback to assign slave port ch_rate
* as master port uses same ch_rate as slave
* unlike soundwire TX master ports where
* unified ports and multiple slave port
* channels can attach to same master port
*/
mport->ch_rate = portinfo->ch_rate[i];
}
}
master->num_port += portinfo->num_port;