diff --git a/drivers/platform/msm/mhi_dev/mhi.c b/drivers/platform/msm/mhi_dev/mhi.c
index ec01ffd037f0..f93ed5a83761 100644
--- a/drivers/platform/msm/mhi_dev/mhi.c
+++ b/drivers/platform/msm/mhi_dev/mhi.c
@@ -3397,12 +3397,11 @@ static int mhi_dev_recover(struct mhi_dev *mhi)
 static void mhi_dev_enable(struct work_struct *work)
 {
 	int rc = 0;
-	struct ep_pcie_msi_config msi_cfg;
 	struct mhi_dev *mhi = container_of(work,
 				struct mhi_dev, ring_init_cb_work);
 	u32 mhi_reset;
 	enum mhi_dev_state state;
-	uint32_t max_cnt = 0, bhi_intvec = 0;
+	uint32_t max_cnt = 0;
 
 	if (mhi->use_ipa) {
 		rc = ipa_dma_init();
@@ -3424,23 +3423,6 @@ static void mhi_dev_enable(struct work_struct *work)
 		return;
 	}
 
-	rc = mhi_dev_mmio_read(mhi, BHI_INTVEC, &bhi_intvec);
-	if (rc)
-		return;
-
-	if (bhi_intvec != 0xffffffff) {
-		/* Indicate the host that the device is ready */
-		rc = ep_pcie_get_msi_config(mhi->phandle, &msi_cfg);
-		if (!rc) {
-			rc = ep_pcie_trigger_msi(mhi_ctx->phandle, bhi_intvec);
-			if (rc) {
-				pr_err("%s: error sending msi\n", __func__);
-				return;
-			}
-		} else {
-			pr_err("MHI: error geting msi configs\n");
-		}
-	}
 
 	rc = mhi_dev_mmio_get_mhi_state(mhi, &state, &mhi_reset);
 	if (rc) {
diff --git a/drivers/platform/msm/mhi_dev/mhi.h b/drivers/platform/msm/mhi_dev/mhi.h
index ab3982a6e329..e73692205307 100644
--- a/drivers/platform/msm/mhi_dev/mhi.h
+++ b/drivers/platform/msm/mhi_dev/mhi.h
@@ -421,7 +421,8 @@ static inline void mhi_dev_ring_inc_index(struct mhi_dev_ring *ring,
 #define TRACE_DATA_MAX				128
 #define MHI_DEV_DATA_MAX			512
 
-#define MHI_DEV_MMIO_RANGE			0xc80
+#define MHI_DEV_MMIO_RANGE			0xb80
+#define MHI_DEV_MMIO_OFFSET			0x100
 
 struct ring_cache_req {
 	struct completion	*done;
diff --git a/drivers/platform/msm/mhi_dev/mhi_mmio.c b/drivers/platform/msm/mhi_dev/mhi_mmio.c
index 44030cee6c93..b0cc8673fe03 100644
--- a/drivers/platform/msm/mhi_dev/mhi_mmio.c
+++ b/drivers/platform/msm/mhi_dev/mhi_mmio.c
@@ -598,18 +598,23 @@ int mhi_dev_restore_mmio(struct mhi_dev *dev)
 	mhi_dev_mmio_mask_interrupts(dev);
 
 	for (i = 0; i < (MHI_DEV_MMIO_RANGE/4); i++) {
-		reg_cntl_addr = dev->mmio_base_addr + (i * 4);
+		reg_cntl_addr = dev->mmio_base_addr +
+				MHI_DEV_MMIO_OFFSET + (i * 4);
 		reg_cntl_value = dev->mmio_backup[i];
 		writel_relaxed(reg_cntl_value, reg_cntl_addr);
 	}
 
 	mhi_dev_mmio_clear_interrupts(dev);
+
+	/* Mask and enable control interrupt */
 	mhi_dev_mmio_enable_ctrl_interrupt(dev);
 
 	/*Enable chdb interrupt*/
 	mhi_dev_mmio_enable_chdb_interrupts(dev);
 
-	/* Mask and enable control interrupt */
+	/*Enable cmdb interrupt*/
+	mhi_dev_mmio_enable_cmdb_interrupt(dev);
+
 	mb();
 
 	return 0;
@@ -619,13 +624,16 @@ EXPORT_SYMBOL(mhi_dev_restore_mmio);
 int mhi_dev_backup_mmio(struct mhi_dev *dev)
 {
 	uint32_t i = 0;
+	void __iomem *reg_cntl_addr;
 
 	if (WARN_ON(!dev))
 		return -EINVAL;
 
-	for (i = 0; i < MHI_DEV_MMIO_RANGE/4; i++)
-		dev->mmio_backup[i] =
-				readl_relaxed(dev->mmio_base_addr + (i * 4));
+	for (i = 0; i < MHI_DEV_MMIO_RANGE/4; i++) {
+		reg_cntl_addr = (void __iomem *) (dev->mmio_base_addr +
+				MHI_DEV_MMIO_OFFSET + (i * 4));
+		dev->mmio_backup[i] = readl_relaxed(reg_cntl_addr);
+	}
 
 	return 0;
 }