From 1d01b6c5e1649a00d90f4d2fbe5e805391d09466 Mon Sep 17 00:00:00 2001 From: Srihitha Tangudu Date: Fri, 22 Apr 2022 13:31:44 +0530 Subject: [PATCH 1/2] disp: msm: dsi: Handle absence of dsi select clocks in device-tree Initialize pll clocks to NULL and warn if dsi select clocks are not defined in device-tree. Change-Id: If831692021278b020d49c06c3bb15d631c0376a4 Signed-off-by: Srihitha Tangudu --- msm/dsi/dsi_display.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index 3e10738546bc..229643bf9b88 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -3558,6 +3558,12 @@ static int dsi_display_clocks_init(struct dsi_display *display) num_clk = dsi_display_get_clocks_count(display, dsi_clock_name); + if (num_clk <= 0) { + rc = num_clk; + DSI_WARN("failed to read %s, rc = %d\n", dsi_clock_name, num_clk); + goto error; + } + DSI_DEBUG("clk count=%d\n", num_clk); for (i = 0; i < num_clk; i++) { From d538367ebd20fbf9c2adb96efd0457487c6b0b28 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Wed, 26 Oct 2022 15:50:44 +0530 Subject: [PATCH 2/2] disp: rsc: update mode-1 threshold config to 1 hz Update mode-1 threshold configuration to 1 hz to avoid selecting mode-2 if panel vsync is irregular. Change-Id: I9d48d088ac1e84f9d0e422d006458527e1944ed8 Signed-off-by: Dhaval Patel Signed-off-by: Mahadevan --- msm/sde_rsc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/msm/sde_rsc.c b/msm/sde_rsc.c index 82aff0540f4d..6e5e3d33adf1 100644 --- a/msm/sde_rsc.c +++ b/msm/sde_rsc.c @@ -368,9 +368,8 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc, rsc_time_slot_0_ns = div_u64(rsc_time_slot_0_ns, cxo_period_ns); rsc->timer_config.rsc_time_slot_0_ns = (u32) rsc_time_slot_0_ns; - /* time_slot_1 for mode1 latency */ - rsc_time_slot_1_ns = frame_time_ns; - rsc_time_slot_1_ns = div_u64(rsc_time_slot_1_ns, cxo_period_ns); + /* time_slot_1 for mode1 latency - 1 fps */ + rsc_time_slot_1_ns = div_u64(TICKS_IN_NANO_SECOND, cxo_period_ns); rsc->timer_config.rsc_time_slot_1_ns = (u32) rsc_time_slot_1_ns; /* mode 2 is infinite */