From afad1f578d6245919a38879b93efde7f366c87e7 Mon Sep 17 00:00:00 2001
From: Udipto Goswami <ugoswami@qti.qualcomm.com>
Date: Mon, 12 Oct 2020 11:45:28 +0530
Subject: [PATCH] ARM: dts: msm: Add secondary controller USB nodes for Yupik

Add secondary controller nodes to support usb on peripheral
mode for Yupik.

Change-Id: Ic8a80b80e7b733f41dec5ced52978060777d7504
---
 qcom/yupik-rumi.dtsi | 25 ++++++++++++++++++
 qcom/yupik-usb.dtsi  | 63 +++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 87 insertions(+), 1 deletion(-)

diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi
index 33c0546db1eb..214eb9eb7441 100644
--- a/qcom/yupik-rumi.dtsi
+++ b/qcom/yupik-rumi.dtsi
@@ -28,6 +28,21 @@
 				     0x0 0x4>;
 	};
 
+	usb_emu_phy_1: usb_emu_phy@8c0e000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x08c0e000 0x9500>;
+
+		qcom,emu-init-seq = <0xffff 0x4
+				     0xfff0 0x4
+				     0x100000 0x20
+				     0x0 0x20
+				     0x101f0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x10060 0x3c
+				     0x0 0x4>;
+	};
+
 	bi_tcxo: bi_tcxo {
 		compatible = "fixed-factor-clock";
 		clock-mult = <1>;
@@ -43,6 +58,7 @@
 		clocks = <&xo_board>;
 		#clock-cells = <0>;
 	};
+
 };
 
 &usb0 {
@@ -54,6 +70,15 @@
 	};
 };
 
+&usb1 {
+	/delete-property/ extcon;
+	dwc3@8c00000 {
+		usb-phy = <&usb_emu_phy_1>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+		dr_mode = "peripheral";
+	};
+};
+
 &sdhc_1 {
 	status = "disabled";
 
diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi
index 0d8f7d16b223..829de6693452 100644
--- a/qcom/yupik-usb.dtsi
+++ b/qcom/yupik-usb.dtsi
@@ -45,7 +45,7 @@
 
 		dwc3@a600000 {
 			compatible = "snps,dwc3";
-			reg = <0xa600000 0xcd00>;
+			reg = <0xa600000 0xe000>;
 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 			linux,sysdev_is_parent;
 			snps,disable-clk-gating;
@@ -62,6 +62,67 @@
 		};
 	};
 
+	usb1: hsusb@8c00000 {
+		status = "disabled";
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x8c00000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_RISING>,
+			     <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 13 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>;
+		clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+			<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_SEC_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk","bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_SEC_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <120000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+
+		dwc3@8c00000 {
+			compatible = "snps,dwc3";
+			reg = <0x8c00000 0xe000>;
+			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			snps,is-utmi-l1-suspend;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			tx-fifo-resize;
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+		};
+	};
+
+
 	usb_nop_phy: usb_nop_phy {
 		compatible = "usb-nop-xceiv";
 	};