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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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Fairly small update, but there are some interesting new features.
Common: Optional support for adding a small amount of polling on each HLT
instruction executed in the guest (or equivalent for other architectures).
This can improve latency up to 50% on some scenarios (e.g. O_DSYNC writes
or TCP_RR netperf tests). This also has to be enabled manually for now,
but the plan is to auto-tune this in the future.
ARM/ARM64: the highlights are support for GICv3 emulation and dirty page
tracking
s390: several optimizations and bugfixes. Also a first: a feature
exposed by KVM (UUID and long guest name in /proc/sysinfo) before
it is available in IBM's hypervisor! :)
MIPS: Bugfixes.
x86: Support for PML (page modification logging, a new feature in
Broadwell Xeons that speeds up dirty page tracking), nested virtualization
improvements (nested APICv---a nice optimization), usual round of emulation
fixes. There is also a new option to reduce latency of the TSC deadline
timer in the guest; this needs to be tuned manually.
Some commits are common between this pull and Catalin's; I see you
have already included his tree.
ARM has other conflicts where functions are added in the same place
by 3.19-rc and 3.20 patches. These are not large though, and entirely
within KVM.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
Pull KVM update from Paolo Bonzini:
"Fairly small update, but there are some interesting new features.
Common:
Optional support for adding a small amount of polling on each HLT
instruction executed in the guest (or equivalent for other
architectures). This can improve latency up to 50% on some
scenarios (e.g. O_DSYNC writes or TCP_RR netperf tests). This
also has to be enabled manually for now, but the plan is to
auto-tune this in the future.
ARM/ARM64:
The highlights are support for GICv3 emulation and dirty page
tracking
s390:
Several optimizations and bugfixes. Also a first: a feature
exposed by KVM (UUID and long guest name in /proc/sysinfo) before
it is available in IBM's hypervisor! :)
MIPS:
Bugfixes.
x86:
Support for PML (page modification logging, a new feature in
Broadwell Xeons that speeds up dirty page tracking), nested
virtualization improvements (nested APICv---a nice optimization),
usual round of emulation fixes.
There is also a new option to reduce latency of the TSC deadline
timer in the guest; this needs to be tuned manually.
Some commits are common between this pull and Catalin's; I see you
have already included his tree.
Powerpc:
Nothing yet.
The KVM/PPC changes will come in through the PPC maintainers,
because I haven't received them yet and I might end up being
offline for some part of next week"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (130 commits)
KVM: ia64: drop kvm.h from installed user headers
KVM: x86: fix build with !CONFIG_SMP
KVM: x86: emulate: correct page fault error code for NoWrite instructions
KVM: Disable compat ioctl for s390
KVM: s390: add cpu model support
KVM: s390: use facilities and cpu_id per KVM
KVM: s390/CPACF: Choose crypto control block format
s390/kernel: Update /proc/sysinfo file with Extended Name and UUID
KVM: s390: reenable LPP facility
KVM: s390: floating irqs: fix user triggerable endless loop
kvm: add halt_poll_ns module parameter
kvm: remove KVM_MMIO_SIZE
KVM: MIPS: Don't leak FPU/DSP to guest
KVM: MIPS: Disable HTW while in guest
KVM: nVMX: Enable nested posted interrupt processing
KVM: nVMX: Enable nested virtual interrupt delivery
KVM: nVMX: Enable nested apic register virtualization
KVM: nVMX: Make nested control MSRs per-cpu
KVM: nVMX: Enable nested virtualize x2apic mode
KVM: nVMX: Prepare for using hardware MSR bitmap
...
This commit is contained in:
Linus Torvalds
commit
b9085bcbf5
88 changed files with 6026 additions and 1626 deletions
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@ -33,6 +33,7 @@
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#define GICD_SETSPI_SR 0x0050
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#define GICD_CLRSPI_SR 0x0058
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#define GICD_SEIR 0x0068
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ISPENDR 0x0200
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@ -41,14 +42,37 @@
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#define GICD_ICACTIVER 0x0380
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#define GICD_IPRIORITYR 0x0400
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#define GICD_ICFGR 0x0C00
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#define GICD_IGRPMODR 0x0D00
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#define GICD_NSACR 0x0E00
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#define GICD_IROUTER 0x6000
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#define GICD_IDREGS 0xFFD0
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#define GICD_PIDR2 0xFFE8
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/*
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* Those registers are actually from GICv2, but the spec demands that they
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* are implemented as RES0 if ARE is 1 (which we do in KVM's emulated GICv3).
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*/
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#define GICD_ITARGETSR 0x0800
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#define GICD_SGIR 0x0F00
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#define GICD_CPENDSGIR 0x0F10
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#define GICD_SPENDSGIR 0x0F20
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_DS (1U << 6)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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/*
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* In systems with a single security state (what we emulate in KVM)
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* the meaning of the interrupt group enable bits is slightly different
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*/
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#define GICD_CTLR_ENABLE_SS_G1 (1U << 1)
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#define GICD_CTLR_ENABLE_SS_G0 (1U << 0)
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#define GICD_TYPER_LPIS (1U << 17)
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#define GICD_TYPER_MBIS (1U << 16)
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#define GICD_TYPER_ID_BITS(typer) ((((typer) >> 19) & 0x1f) + 1)
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#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_TYPER_LPIS (1U << 17)
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@ -60,6 +84,8 @@
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#define GIC_PIDR2_ARCH_GICv3 0x30
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#define GIC_PIDR2_ARCH_GICv4 0x40
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#define GIC_V3_DIST_SIZE 0x10000
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/*
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* Re-Distributor registers, offsets from RD_base
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*/
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@ -78,6 +104,7 @@
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#define GICR_SYNCR 0x00C0
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#define GICR_MOVLPIR 0x0100
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#define GICR_MOVALLR 0x0110
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#define GICR_IDREGS GICD_IDREGS
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#define GICR_PIDR2 GICD_PIDR2
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#define GICR_CTLR_ENABLE_LPIS (1UL << 0)
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@ -104,6 +131,7 @@
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/*
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* Re-Distributor registers, offsets from SGI_base
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*/
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#define GICR_IGROUPR0 GICD_IGROUPR
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#define GICR_ISENABLER0 GICD_ISENABLER
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#define GICR_ICENABLER0 GICD_ICENABLER
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#define GICR_ISPENDR0 GICD_ISPENDR
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@ -112,11 +140,15 @@
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#define GICR_ICACTIVER0 GICD_ICACTIVER
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#define GICR_IPRIORITYR0 GICD_IPRIORITYR
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#define GICR_ICFGR0 GICD_ICFGR
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#define GICR_IGRPMODR0 GICD_IGRPMODR
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#define GICR_NSACR GICD_NSACR
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#define GICR_TYPER_PLPIS (1U << 0)
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#define GICR_TYPER_VLPIS (1U << 1)
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#define GICR_TYPER_LAST (1U << 4)
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#define GIC_V3_REDIST_SIZE 0x20000
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#define LPI_PROP_GROUP1 (1 << 1)
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#define LPI_PROP_ENABLED (1 << 0)
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@ -248,6 +280,18 @@
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#define ICC_SRE_EL2_SRE (1 << 0)
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#define ICC_SRE_EL2_ENABLE (1 << 3)
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#define ICC_SGI1R_TARGET_LIST_SHIFT 0
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#define ICC_SGI1R_TARGET_LIST_MASK (0xffff << ICC_SGI1R_TARGET_LIST_SHIFT)
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#define ICC_SGI1R_AFFINITY_1_SHIFT 16
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#define ICC_SGI1R_AFFINITY_1_MASK (0xff << ICC_SGI1R_AFFINITY_1_SHIFT)
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#define ICC_SGI1R_SGI_ID_SHIFT 24
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#define ICC_SGI1R_SGI_ID_MASK (0xff << ICC_SGI1R_SGI_ID_SHIFT)
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#define ICC_SGI1R_AFFINITY_2_SHIFT 32
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#define ICC_SGI1R_AFFINITY_2_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
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#define ICC_SGI1R_IRQ_ROUTING_MODE_BIT 40
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#define ICC_SGI1R_AFFINITY_3_SHIFT 48
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#define ICC_SGI1R_AFFINITY_3_MASK (0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)
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/*
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* System register definitions
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*/
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@ -33,10 +33,6 @@
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#include <asm/kvm_host.h>
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#ifndef KVM_MMIO_SIZE
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#define KVM_MMIO_SIZE 8
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#endif
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/*
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* The bit 16 ~ bit 31 of kvm_memory_region::flags are internally used
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* in kvm, other bits are visible for userspace which are defined in
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@ -600,6 +596,15 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext);
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int kvm_get_dirty_log(struct kvm *kvm,
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struct kvm_dirty_log *log, int *is_dirty);
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int kvm_get_dirty_log_protect(struct kvm *kvm,
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struct kvm_dirty_log *log, bool *is_dirty);
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void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
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struct kvm_memory_slot *slot,
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gfn_t gfn_offset,
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unsigned long mask);
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int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
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struct kvm_dirty_log *log);
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@ -641,7 +646,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
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void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu);
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struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id);
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int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu);
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int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu);
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void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu);
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int kvm_arch_hardware_enable(void);
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@ -1031,6 +1036,8 @@ void kvm_unregister_device_ops(u32 type);
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extern struct kvm_device_ops kvm_mpic_ops;
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extern struct kvm_device_ops kvm_xics_ops;
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extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
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extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
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#ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
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