From b92c3f5e10b6dca5075acd6702b6d4b1041cb485 Mon Sep 17 00:00:00 2001 From: Mayank Rana Date: Wed, 3 Jun 2020 15:58:31 -0700 Subject: [PATCH] ARM: dts: msm: Add USB CSR clock entry on Lahaina USB CSR clock is required to keep ON for retaining USB controller CSR while going into CXPC. Hence add USB CSR clock entries with primary and secondary USB controller to support USB host mode bus suspend usecase. Change-Id: I1fe6dbedbb434a546fd719232411d37902b88f70 --- qcom/lahaina-usb.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 9c09ccf129f4..2203e29cf41d 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -29,9 +29,10 @@ <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>; + <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&clock_gcc GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk"; + "utmi_clk", "sleep_clk", "core_csr_clk"; resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; @@ -355,9 +356,10 @@ <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, - <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; + <&clock_gcc GCC_USB3_SEC_CLKREF_EN>, + <&clock_gcc GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk", "xo"; + "utmi_clk", "sleep_clk", "xo", "core_csr_clk"; resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset";