diff --git a/include/soc/soundwire.h b/include/soc/soundwire.h
index abb078fdb09d..279642816072 100644
--- a/include/soc/soundwire.h
+++ b/include/soc/soundwire.h
@@ -77,6 +77,8 @@ struct swr_port_info {
 	u8 hstop;
 	u8 blk_grp_count;
 	u8 blk_pack_mode;
+	u8 word_length;
+	u8 lane_ctrl;
 	u8 ch_en;
 	u8 req_ch;
 	u8 num_ch;
diff --git a/soc/swrm_registers.h b/soc/swrm_registers.h
index f1d2586944b2..0147e459d76d 100644
--- a/soc/swrm_registers.h
+++ b/soc/swrm_registers.h
@@ -179,6 +179,30 @@
 #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT		0x08
 #define SWRM_DP_PORT_CTRL_SAMPLE_INTERVAL	0x00
 
+#define SWRM_DP_PORT_CTRL_2_BANK(n, m)	(SWRM_BASE_ADDRESS + \
+							0x00001128 + \
+							0x100*(n-1) + \
+							0x40*m)
+
+#define SWRM_DP_BLOCK_CTRL_1(n)		(SWRM_BASE_ADDRESS + \
+							0x0000112C + 0x100*n)
+
+#define SWRM_DP_BLOCK_CTRL2_BANK(n, m)	(SWRM_BASE_ADDRESS + \
+							0x00001130 + \
+							0x100*(n-1) + \
+							0x40*m)
+
+#define SWRM_DP_PORT_HCTRL_BANK(n, m)	(SWRM_BASE_ADDRESS + \
+							0x00001134 + \
+							0x100*(n-1) + \
+							0x40*m)
+
+#define SWRM_DP_BLOCK_CTRL3_BANK(n, m)	(SWRM_BASE_ADDRESS + \
+							0x00001138 + \
+							0x100*(n-1) + \
+							0x40*m)
+
+
 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (SWRM_BASE_ADDRESS + \
 						0x00001054 + 0x100*n)
 
@@ -190,8 +214,14 @@
 
 #define SWRS_DP_REG_OFFSET(port, bank)		((0x100*port)+(0x10*bank))
 
+#define SWRS_SCP_CONTROL				0x44
+#define SWRS_DP_BLOCK_CONTROL_1(n)		(SWRS_BASE_ADDRESS + 0x120 + \
+						0x100 * n)
+
 #define SWRS_DP_CHANNEL_ENABLE_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x120 + \
 						 SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_BLOCK_CONTROL_2_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x121 + \
+						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x122 + \
 						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x124 + \
@@ -202,6 +232,8 @@
 						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_BLOCK_CONTROL_3_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x127 + \
 						 SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_LANE_CONTROL_BANK(n, m) (SWRS_BASE_ADDRESS + 0x128 + \
+						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_SCP_FRAME_CTRL_BANK(m)		(SWRS_BASE_ADDRESS + 0x60 + \
 						 0x10*m)
 #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m)	(SWRS_BASE_ADDRESS + 0xE0 + \