From b978901b76c70b159a056ee5508cf3c4ae805fd0 Mon Sep 17 00:00:00 2001
From: Raghu Ananya Arabolu <rarabolu@quicinc.com>
Date: Thu, 28 May 2020 18:39:25 -0700
Subject: [PATCH] ARM: dts: msm: Add GPU power levels for Lahaina r2

Add the GPU power levels for Lahaina r2 configuration.

Change-Id: I1d7b75cee6ebbbe2d8fb364e3f2485855b6885e4
---
 qcom/lahaina-v2-gpu.dtsi | 94 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi
index 1318a9d2c4a6..d965798f77cd 100644
--- a/qcom/lahaina-v2-gpu.dtsi
+++ b/qcom/lahaina-v2-gpu.dtsi
@@ -1,3 +1,97 @@
 &msm_gpu {
 	qcom,chipid = <0x06060001>;
+
+	qcom,initial-pwrlevel = <5>;
+
+	/* Power levels */
+	qcom,gpu-pwrlevels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		compatible = "qcom,gpu-pwrlevels";
+
+		qcom,gpu-pwrlevel@0 {
+			reg = <0>;
+			qcom,gpu-freq = <738000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+			qcom,bus-freq-ddr7 = <11>;
+			qcom,bus-min-ddr7 = <11>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <11>;
+			qcom,bus-min-ddr8 = <11>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <676000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
+
+			qcom,bus-freq-ddr7 = <11>;
+			qcom,bus-min-ddr7 = <11>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <10>;
+			qcom,bus-min-ddr8 = <10>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
+			qcom,gpu-freq = <608000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+
+			qcom,bus-freq-ddr7 = <8>;
+			qcom,bus-min-ddr7 = <7>;
+			qcom,bus-max-ddr7 = <11>;
+
+			qcom,bus-freq-ddr8 = <7>;
+			qcom,bus-min-ddr8 = <7>;
+			qcom,bus-max-ddr8 = <11>;
+		};
+
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
+			qcom,gpu-freq = <540000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+
+			qcom,bus-freq-ddr7 = <8>;
+			qcom,bus-min-ddr7 = <7>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <7>;
+			qcom,bus-min-ddr8 = <7>;
+			qcom,bus-max-ddr8 = <9>;
+		};
+
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
+			qcom,gpu-freq = <443000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
+
+			qcom,bus-freq-ddr7 = <8>;
+			qcom,bus-min-ddr7 = <6>;
+			qcom,bus-max-ddr7 = <10>;
+
+			qcom,bus-freq-ddr8 = <7>;
+			qcom,bus-min-ddr8 = <6>;
+			qcom,bus-max-ddr8 = <9>;
+		};
+
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
+			qcom,gpu-freq = <315000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+
+			qcom,bus-freq-ddr7 = <3>;
+			qcom,bus-min-ddr7 = <3>;
+			qcom,bus-max-ddr7 = <9>;
+
+			qcom,bus-freq-ddr8 = <3>;
+			qcom,bus-min-ddr8 = <3>;
+			qcom,bus-max-ddr8 = <8>;
+		};
+	};
 };