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irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

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When EIC mode is in use (cpu_has_veic is true) enable it on each CPU
during GIC initialisation. Otherwise there may be a mismatch between the
hardware default interrupt model & that expected by the kernel.

Signed-off-by: Paul Burton <[email protected]>
Reviewed-by: Matt Redfearn <[email protected]>
Tested-by: Matt Redfearn <[email protected]>
Acked-by: Thomas Gleixner <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/13274/
Signed-off-by: Ralf Baechle <[email protected]>
This commit is contained in:
Paul Burton 2016-05-17 15:31:06 +01:00 • committed by Ralf Baechle
commit ba01cf0e12
1 changed files with 9 additions and 1 deletions
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10
drivers/irqchip/irq-mips-gic.c
View file

@ -968,7 +968,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
unsigned int cpu_vec, unsigned int irqbase,
struct device_node *node)
{
unsigned int gicconfig;
unsigned int gicconfig, cpu;
unsigned int v[2];
__gic_base_addr = gic_base_addr;
@ -985,6 +985,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
gic_vpes = gic_vpes + 1;
if (cpu_has_veic) {
/* Set EIC mode for all VPEs */
for_each_present_cpu(cpu) {
gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
mips_cm_vp_id(cpu));
gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
GIC_VPE_CTL_EIC_MODE_MSK);
}
/* Always use vector 1 in EIC mode */
gic_cpu_pin = 0;
timer_cpu_pin = gic_cpu_pin;