From 51e30024ecf164881e06ec70aa3ca95768a9aa3d Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Mon, 13 Apr 2020 16:51:51 -0700 Subject: [PATCH 1/2] interconnect: qcom: lahaina: Enable the rest of the QoS ports Enable QoS configuration for the the rest of the QoS ports, including IPA and the second MMNOC ports. Change-Id: I1ff839f5f1d422eb1170b1bf94a6d375e61eeb5d Signed-off-by: Mike Tipton --- drivers/interconnect/qcom/lahaina.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/interconnect/qcom/lahaina.c b/drivers/interconnect/qcom/lahaina.c index a5e926154844..15ac39dbede1 100644 --- a/drivers/interconnect/qcom/lahaina.c +++ b/drivers/interconnect/qcom/lahaina.c @@ -36,7 +36,7 @@ DEFINE_QNODE_QOS(qhm_qdss_bam, 2, 0, 1, 98304); DEFINE_QNODE_QOS(qhm_qup0, 2, 0, 1, 102400); DEFINE_QNODE_QOS(qhm_qup2, 2, 0, 1, 106496); DEFINE_QNODE_QOS(qxm_crypto, 2, 1, 1, 118784); -DEFINE_QNODE_QOS(qxm_ipa, 2, 1, 0, 65536); +DEFINE_QNODE_QOS(qxm_ipa, 2, 1, 1, 65536); DEFINE_QNODE_QOS(xm_pcie3_0, 2, 0, 1, 77824); DEFINE_QNODE_QOS(xm_pcie3_1, 2, 0, 1, 81920); DEFINE_QNODE_QOS(xm_qdss_etr, 2, 0, 1, 86016); @@ -46,8 +46,8 @@ DEFINE_QNODE_QOS(alm_gpu_tcu, 1, 0, 1, 655360); DEFINE_QNODE_QOS(alm_sys_tcu, 6, 0, 1, 659456); DEFINE_QNODE_QOS(qnm_cmpnoc, 0, 1, 2, 135168, 397312); DEFINE_QNODE_QOS(qnm_gpu, 0, 0, 2, 139264, 401408); -DEFINE_QNODE_QOS(qnm_mnoc_hf, 0, 1, 1, 143360, 405504); -DEFINE_QNODE_QOS(qnm_mnoc_sf, 0, 1, 1, 147456, 409600); +DEFINE_QNODE_QOS(qnm_mnoc_hf, 0, 1, 2, 143360, 405504); +DEFINE_QNODE_QOS(qnm_mnoc_sf, 0, 1, 2, 147456, 409600); DEFINE_QNODE_QOS(qnm_pcie, 2, 1, 1, 663552); DEFINE_QNODE_QOS(qnm_snoc_gc, 0, 1, 1, 667648); DEFINE_QNODE_QOS(qnm_snoc_sf, 0, 1, 1, 671744); From bd541f74525ad7c8952ef946fe93d13587584a42 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Mon, 13 Apr 2020 16:55:18 -0700 Subject: [PATCH 2/2] interconnect: qcom: lahaina: Use the correct binding for qnm_pcie Use the correct dt-binding for qnm_pcie in the node lookup array. The specific array index is only important for the xlate() callback. Using the wrong binding means of_icc_get() will fail for any clients attempting to get a phandle to MASTER_ANOC_PCIE_GEM_NOC in devicetree. However, even with the wrong array index the node will still be registered and paths through this node will still function properly. Change-Id: I484461020b39e68c380fa5a26078ed9712c93e4c Signed-off-by: Mike Tipton --- drivers/interconnect/qcom/lahaina.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/interconnect/qcom/lahaina.c b/drivers/interconnect/qcom/lahaina.c index 15ac39dbede1..e9c5cf28d9c5 100644 --- a/drivers/interconnect/qcom/lahaina.c +++ b/drivers/interconnect/qcom/lahaina.c @@ -669,7 +669,7 @@ static struct qcom_icc_node *gem_noc_nodes[] = { [MASTER_GFX3D] = &qnm_gpu, [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, - [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, + [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,