From 2e55bc6bef9a16f4e30909ad1f03433a63b811e4 Mon Sep 17 00:00:00 2001
From: Madhuri Medasani <mmedasan@qti.qualcomm.com>
Date: Wed, 7 Apr 2021 18:01:28 +0530
Subject: [PATCH] ARM: dts: msm: Add support for clock controllers for BLAIR

Enable GPUCC, DISPCC and DEBUGCC and update RPMCC
to use holi-rpmcc instead of dummy for BLAIR RUMI.

Change-Id: Ia3aa16e4181aa3e2760eb2981af24c6111d27a32
---
 qcom/blair-rumi.dtsi | 30 ------------------------------
 qcom/blair.dtsi      |  9 +++------
 2 files changed, 3 insertions(+), 36 deletions(-)

diff --git a/qcom/blair-rumi.dtsi b/qcom/blair-rumi.dtsi
index 22df7e1574e2..23e168b9326c 100644
--- a/qcom/blair-rumi.dtsi
+++ b/qcom/blair-rumi.dtsi
@@ -1,5 +1,4 @@
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clock/qcom,gcc-blair.h>
 &soc {
 	timer {
 		clock-frequency = <500000>;
@@ -27,22 +26,6 @@
 				     0x10060 0x3c
 				     0x0 0x4>;
 	};
-
-	bi_tcxo: bi_tcxo {
-		compatible = "fixed-factor-clock";
-		clock-mult = <1>;
-		clock-div = <2>;
-		clocks = <&xo_board>;
-		#clock-cells = <0>;
-	 };
-
-	bi_tcxo_ao: bi_tcxo_ao {
-		compatible = "fixed-factor-clock";
-		clock-mult = <1>;
-		clock-div = <2>;
-		clocks = <&xo_board>;
-		#clock-cells = <0>;
-	};
 };
 
 &tsens0 {
@@ -142,15 +125,6 @@
 	rpm-standalone;
 };
 
-&rpmcc {
-	compatible = "qcom,dummycc";
-	clock-output-names = "rpmhcc_clocks";
-};
-
-&gcc {
-	clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
-};
-
 &usb0 {
 	dwc3@4e00000 {
 		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
@@ -158,7 +132,3 @@
 		dr_mode = "peripheral";
 	};
 };
-
-&cpufreq_hw {
-	clocks = <&bi_tcxo>, <&gcc GPLL0>;
-};
diff --git a/qcom/blair.dtsi b/qcom/blair.dtsi
index d07cff003c66..218dfa212f0e 100644
--- a/qcom/blair.dtsi
+++ b/qcom/blair.dtsi
@@ -1214,7 +1214,7 @@
 	};
 
 	dispcc: clock-controller@5f00000 {
-		compatible = "qcom,holi-dispcc", "syscon";
+		compatible = "qcom,blair-dispcc", "syscon";
 		reg = <0x5f00000 0x20000>;
 		reg-names = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1223,11 +1223,10 @@
 		clock-names = "bi_tcxo", "gcc_disp_gpll0_clk";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		status = "disabled";
 	};
 
 	gpucc: clock-controller@5990000 {
-		compatible = "qcom,holi-gpucc", "syscon";
+		compatible = "qcom,blair-gpucc", "syscon";
 		reg = <0x5990000 0x9000>;
 		reg-names = "cc_base";
 		vdd_cx-supply = <&VDD_CX_LEVEL>;
@@ -1241,7 +1240,6 @@
 				"gcc_gpu_snoc_dvm_gfx_clk";
 		#clock-cells = <1>;
 		#reset-cells = <1>;
-		status = "disabled";
 	};
 
 	cpucc: syscon@faa0018 {
@@ -1255,7 +1253,7 @@
 	};
 
 	debugcc: clock-controller@0 {
-		compatible = "qcom,holi-debugcc";
+		compatible = "qcom,blair-debugcc";
 		qcom,gcc = <&gcc>;
 		qcom,dispcc = <&dispcc>;
 		qcom,gpucc = <&gpucc>;
@@ -1264,7 +1262,6 @@
 		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
 		clock-names = "xo_clk_src";
 		#clock-cells = <1>;
-		status = "disabled";
 	};
 
 	cpufreq_hw: qcom,cpufreq-hw {