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msm: kgsl: Finish up the last bits of the perfcounter transition

Browse source 
Now that all the perfcounter code is safely target specific finish up the
transition. First move the perfcounter definition from the gpudev to the
adreno_gpu_core so that we can specify the list per target which gives us
more control than modifying the gpudev at runtime or creating multiple
gpudev structs just for the perfcounter deltas.

Further drive home the point by marking the perfcounter and groups
as const. The perfcounter migration has now completed. You don't have
to go home, but you can't stay here.

Change-Id: Ic0dedbad4b4dbb8e9e49ed94dc23b97fc578324b
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This commit is contained in:
Jordan Crouse 2020-05-14 19:32:46 -06:00
commit ba7d8b8807
14 changed files with 111 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

27
drivers/gpu/msm/adreno-gpulist.h
View file

@ -26,6 +26,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306 = {
DEFINE_ADRENO_REV(ADRENO_REV_A306, 3, 0, 6, 0),
.features = ADRENO_SOFT_FAULT_DETECT,
.gpudev = &adreno_a3xx_gpudev,
.perfcounters = &adreno_a3xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_128K,
.bus_width = 0,
@ -48,6 +49,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a306a = {
DEFINE_ADRENO_REV(ADRENO_REV_A306A, 3, 0, 6, 0x20),
.features = ADRENO_SOFT_FAULT_DETECT,
.gpudev = &adreno_a3xx_gpudev,
.perfcounters = &adreno_a3xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_128K,
.bus_width = 16,
@ -68,6 +70,7 @@ static const struct adreno_a3xx_core adreno_gpu_core_a304 = {
DEFINE_ADRENO_REV(ADRENO_REV_A304, 3, 0, 4, 0),
.features = ADRENO_SOFT_FAULT_DETECT,
.gpudev = &adreno_a3xx_gpudev,
.perfcounters = &adreno_a3xx_perfcounters,
.gmem_base = 0,
.gmem_size = (SZ_64K + SZ_32K),
.bus_width = 0,
@ -192,6 +195,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v2 = {
ADRENO_PREEMPTION |
ADRENO_CONTENT_PROTECTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_1M,
.bus_width = 32,
@ -218,6 +222,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a530v3 = {
ADRENO_PREEMPTION |
ADRENO_CONTENT_PROTECTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_1M,
.bus_width = 32,
@ -284,6 +289,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a505 = {
DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
.features = ADRENO_PREEMPTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_8K),
.bus_width = 16,
@ -303,6 +309,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a506 = {
.features = ADRENO_PREEMPTION |
ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_8K),
.bus_width = 16,
@ -381,6 +388,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a510 = {
.base = {
DEFINE_ADRENO_REV(ADRENO_REV_A510, 5, 1, 0, ANY_ID),
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_256K,
.bus_width = 16,
@ -506,6 +514,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a540v2 = {
ADRENO_CONTENT_PROTECTION |
ADRENO_GPMU | ADRENO_SPTP_PC,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_1M,
.bus_width = 32,
@ -589,6 +598,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a512 = {
.features = ADRENO_PREEMPTION |
ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_256K + SZ_16K),
.bus_width = 32,
@ -608,6 +618,7 @@ static const struct adreno_a5xx_core adreno_gpu_core_a508 = {
.features = ADRENO_PREEMPTION |
ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION,
.gpudev = &adreno_a5xx_gpudev,
.perfcounters = &adreno_a5xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_8K),
.bus_width = 32,
@ -783,6 +794,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION |
ADRENO_IOCOHERENT | ADRENO_PREEMPTION,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a630_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_1M,
.bus_width = 32,
@ -882,6 +894,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
ADRENO_IOCOHERENT,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -909,6 +922,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
ADRENO_IOCOHERENT,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -936,6 +950,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619 = {
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
ADRENO_IOCOHERENT,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -962,6 +977,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a619_variant = {
.compatible = "qcom,adreno-gpu-a619-holi",
.features = ADRENO_PREEMPTION | ADRENO_CONTENT_PROTECTION,
.gpudev = &adreno_a619_holi_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -1088,6 +1104,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
ADRENO_APRIV,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -1178,6 +1195,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
ADRENO_CONTENT_PROTECTION | ADRENO_IOCOHERENT |
ADRENO_IFPC | ADRENO_PREEMPTION,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_1M, //Verified 1MB
.bus_width = 32,
@ -1258,6 +1276,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_IFPC | ADRENO_APRIV,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
.bus_width = 32,
@ -1287,6 +1306,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD |
ADRENO_LM | ADRENO_APRIV,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_128K, /* verified 1152kB */
.bus_width = 32,
@ -1313,6 +1333,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
DEFINE_ADRENO_REV(ADRENO_REV_A680, 6, 8, 0, ANY_ID),
.features = ADRENO_RPMH | ADRENO_GPMU,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_2M,
.bus_width = 32,
@ -1390,6 +1411,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |
ADRENO_IFPC,
.gpudev = &adreno_a6xx_rgmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_4K),
.bus_width = 32,
@ -1415,6 +1437,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_IFPC |
ADRENO_IOCOHERENT,
.gpudev = &adreno_a630_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = SZ_512K,
.bus_width = 32,
@ -1441,6 +1464,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a610 = {
.features = ADRENO_CONTENT_PROTECTION |
ADRENO_PREEMPTION,
.gpudev = &adreno_a6xx_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0x100000,
.gmem_size = (SZ_128K + SZ_4K),
.bus_width = 32,
@ -1556,6 +1580,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_IFPC | ADRENO_PREEMPTION,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_512K,
.bus_width = 32,
@ -1587,6 +1612,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660v2 = {
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_IFPC | ADRENO_PREEMPTION | ADRENO_ACD,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_512K,
.bus_width = 32,
@ -1619,6 +1645,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660_shima = {
ADRENO_IOCOHERENT | ADRENO_CONTENT_PROTECTION |
ADRENO_IFPC,
.gpudev = &adreno_a6xx_gmu_gpudev,
.perfcounters = &adreno_a6xx_perfcounters,
.gmem_base = 0,
.gmem_size = SZ_1M + SZ_512K,
.bus_width = 32,

3
drivers/gpu/msm/adreno.h
View file

@ -392,6 +392,7 @@ struct adreno_gpu_core {
const char *compatible;
unsigned long features;
struct adreno_gpudev *gpudev;
const struct adreno_perfcounters *perfcounters;
unsigned long gmem_base;
size_t gmem_size;
u32 bus_width;
@ -762,8 +763,6 @@ struct adreno_gpudev {
const struct adreno_ft_perf_counters *ft_perf_counters;
unsigned int ft_perf_counters_count;
struct adreno_perfcounters *perfcounters;
struct adreno_coresight *coresight[2];
unsigned int vbif_xin_halt_ctrl0_mask;

1
drivers/gpu/msm/adreno_a3xx.c
View file

@ -1236,7 +1236,6 @@ struct adreno_gpudev adreno_a3xx_gpudev = {
.reg_offsets = a3xx_register_offsets,
.ft_perf_counters = a3xx_ft_perf_counters,
.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),
.perfcounters = &adreno_a3xx_perfcounters,
.irq_handler = a3xx_irq_handler,
.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,
.probe = a3xx_probe,

2
drivers/gpu/msm/adreno_a3xx.h
View file

@ -44,6 +44,6 @@ unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev);
void a3xx_snapshot(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot);
extern struct adreno_perfcounters adreno_a3xx_perfcounters;
extern const struct adreno_perfcounters adreno_a3xx_perfcounters;
#endif /*__A3XX_H */

21
drivers/gpu/msm/adreno_a3xx_perfcounter.c
View file

@ -19,7 +19,7 @@
#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
static int a3xx_counter_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -32,7 +32,7 @@ static int a3xx_counter_enable(struct adreno_device *adreno_dev,
}
static u64 a3xx_counter_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -52,14 +52,14 @@ static u64 a3xx_counter_read(struct adreno_device *adreno_dev,
}
static int a3xx_counter_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
return 0;
}
static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -83,7 +83,7 @@ static u64 a3xx_counter_pwr_read(struct adreno_device *adreno_dev,
}
static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -113,7 +113,7 @@ static int a3xx_counter_vbif_enable(struct adreno_device *adreno_dev,
}
static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -133,7 +133,7 @@ static u64 a3xx_counter_vbif_read(struct adreno_device *adreno_dev,
}
static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -154,7 +154,7 @@ static int a3xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
}
static u64 a3xx_counter_vbif_pwr_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -356,7 +356,8 @@ static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = {
#define A3XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read) \
ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, offset, name, flags, enable, read)
static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
static const struct adreno_perfcount_group
a3xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MAX] = {
A3XX_PERFCOUNTER_GROUP(CP, cp,
a3xx_counter_enable, a3xx_counter_read),
A3XX_PERFCOUNTER_GROUP(RBBM, rbbm,
@ -392,7 +393,7 @@ static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {
};
struct adreno_perfcounters adreno_a3xx_perfcounters = {
const struct adreno_perfcounters adreno_a3xx_perfcounters = {
a3xx_perfcounter_groups,
ARRAY_SIZE(a3xx_perfcounter_groups),
};

1
drivers/gpu/msm/adreno_a5xx.c
View file

@ -2648,7 +2648,6 @@ struct adreno_gpudev adreno_a5xx_gpudev = {
.irq_handler = a5xx_irq_handler,
.rb_start = a5xx_rb_start,
.microcode_read = a5xx_microcode_read,
.perfcounters = &adreno_a5xx_perfcounters,
.vbif_xin_halt_ctrl0_mask = A5XX_VBIF_XIN_HALT_CTRL0_MASK,
.is_sptp_idle = a5xx_is_sptp_idle,
.regulator_enable = a5xx_regulator_enable,

2
drivers/gpu/msm/adreno_a5xx.h
View file

@ -239,6 +239,6 @@ void a5xx_preempt_callback(struct adreno_device *adreno_dev, int bit);
u64 a5xx_read_alwayson(struct adreno_device *adreno_dev);
extern struct adreno_perfcounters adreno_a5xx_perfcounters;
extern const struct adreno_perfcounters adreno_a5xx_perfcounters;
#endif

24
drivers/gpu/msm/adreno_a5xx_perfcounter.c
View file

@ -17,7 +17,7 @@
#define VBIF2_PERF_PWR_CLR_REG_EN_OFF 8
static u64 a5xx_counter_read_norestore(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -31,7 +31,7 @@ static u64 a5xx_counter_read_norestore(struct adreno_device *adreno_dev,
}
static int a5xx_counter_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -44,7 +44,7 @@ static int a5xx_counter_enable(struct adreno_device *adreno_dev,
}
static int a5xx_counter_rbbm_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
if (adreno_is_a540(adreno_dev) && countable == A5XX_RBBM_ALWAYS_COUNT)
@ -54,7 +54,7 @@ static int a5xx_counter_rbbm_enable(struct adreno_device *adreno_dev,
}
static u64 a5xx_counter_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -68,7 +68,7 @@ static u64 a5xx_counter_read(struct adreno_device *adreno_dev,
}
static int a5xx_counter_vbif_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -98,7 +98,7 @@ static int a5xx_counter_vbif_enable(struct adreno_device *adreno_dev,
}
static int a5xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -120,14 +120,14 @@ static int a5xx_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
}
static int a5xx_counter_alwayson_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
return 0;
}
static u64 a5xx_counter_alwayson_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct adreno_perfcount_register *reg = &group->regs[counter];
@ -136,7 +136,7 @@ static u64 a5xx_counter_alwayson_read(struct adreno_device *adreno_dev,
}
static int a5xx_counter_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -150,7 +150,7 @@ static int a5xx_counter_pwr_enable(struct adreno_device *adreno_dev,
}
static int a5xx_counter_pwr_gpmu_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -173,7 +173,7 @@ static int a5xx_counter_pwr_gpmu_enable(struct adreno_device *adreno_dev,
}
static int a5xx_counter_pwr_alwayson_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -621,7 +621,7 @@ static struct adreno_perfcount_group a5xx_perfcounter_groups
a5xx_counter_pwr_alwayson_enable, a5xx_counter_read_norestore),
};
struct adreno_perfcounters adreno_a5xx_perfcounters = {
const struct adreno_perfcounters adreno_a5xx_perfcounters = {
a5xx_perfcounter_groups,
ARRAY_SIZE(a5xx_perfcounter_groups),
};

6
drivers/gpu/msm/adreno_a6xx.c
View file

@ -2394,7 +2394,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &adreno_a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,
@ -2424,7 +2423,6 @@ struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
.probe = a6xx_hwsched_probe,
.snapshot = a6xx_hwsched_snapshot,
.irq_handler = a6xx_irq_handler,
.perfcounters = &adreno_a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.iommu_fault_block = a6xx_iommu_fault_block,
.preemption_context_init = a6xx_preemption_context_init,
@ -2446,7 +2444,6 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &adreno_a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,
@ -2478,7 +2475,6 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &adreno_a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,
@ -2510,7 +2506,6 @@ struct adreno_gpudev adreno_a619_holi_gpudev = {
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &adreno_a6xx_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,
@ -2545,7 +2540,6 @@ struct adreno_gpudev adreno_a630_gpudev = {
.rb_start = a6xx_rb_start,
.regulator_enable = a6xx_sptprac_enable,
.regulator_disable = a6xx_sptprac_disable,
.perfcounters = &adreno_a630_perfcounters,
.read_throttling_counters = a6xx_read_throttling_counters,
.microcode_read = a6xx_microcode_read,
.gpu_keepalive = a6xx_gpu_keepalive,

4
drivers/gpu/msm/adreno_a6xx.h
View file

@ -405,6 +405,6 @@ void a6xx_spin_idle_debug(struct adreno_device *adreno_dev,
int a6xx_perfcounter_update(struct adreno_device *adreno_dev,
struct adreno_perfcount_register *reg, bool update_reg);
extern struct adreno_perfcounters adreno_a630_perfcounters;
extern struct adreno_perfcounters adreno_a6xx_perfcounters;
extern const struct adreno_perfcounters adreno_a630_perfcounters;
extern const struct adreno_perfcounters adreno_a6xx_perfcounters;
#endif

28
drivers/gpu/msm/adreno_a6xx_perfcounter.c
View file

@ -34,7 +34,7 @@
* the stored shadow value
*/
static u64 a6xx_counter_read_norestore(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -48,7 +48,7 @@ static u64 a6xx_counter_read_norestore(struct adreno_device *adreno_dev,
}
static int a6xx_counter_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -67,7 +67,7 @@ static int a6xx_counter_enable(struct adreno_device *adreno_dev,
}
static int a6xx_counter_inline_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -130,7 +130,7 @@ static int a6xx_counter_inline_enable(struct adreno_device *adreno_dev,
}
static u64 a6xx_counter_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -145,7 +145,7 @@ static u64 a6xx_counter_read(struct adreno_device *adreno_dev,
}
static int a6xx_counter_gbif_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -176,7 +176,7 @@ static int a6xx_counter_gbif_enable(struct adreno_device *adreno_dev,
}
static int a630_counter_vbif_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -206,7 +206,7 @@ static int a630_counter_vbif_enable(struct adreno_device *adreno_dev,
}
static int a630_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -227,7 +227,7 @@ static int a630_counter_vbif_pwr_enable(struct adreno_device *adreno_dev,
}
static int a6xx_counter_gbif_pwr_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@ -254,14 +254,14 @@ static int a6xx_counter_gbif_pwr_enable(struct adreno_device *adreno_dev,
}
static int a6xx_counter_alwayson_enable(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable)
{
return 0;
}
static u64 a6xx_counter_alwayson_read(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group,
const struct adreno_perfcount_group *group,
unsigned int counter)
{
struct adreno_perfcount_register *reg = &group->regs[counter];
@ -630,7 +630,7 @@ static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = {
#define A6XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags, enable, read) \
ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, flags, enable, read)
static struct adreno_perfcount_group a630_perfcounter_groups
static const struct adreno_perfcount_group a630_perfcounter_groups
[KGSL_PERFCOUNTER_GROUP_MAX] = {
A6XX_PERFCOUNTER_GROUP(CP, cp,
a6xx_counter_enable, a6xx_counter_read),
@ -674,7 +674,7 @@ static struct adreno_perfcount_group a630_perfcounter_groups
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
};
static struct adreno_perfcount_group a6xx_perfcounter_groups
static const struct adreno_perfcount_group a6xx_perfcounter_groups
[KGSL_PERFCOUNTER_GROUP_MAX] = {
A6XX_PERFCOUNTER_GROUP(CP, cp,
a6xx_counter_enable, a6xx_counter_read),
@ -718,12 +718,12 @@ static struct adreno_perfcount_group a6xx_perfcounter_groups
a6xx_counter_alwayson_enable, a6xx_counter_alwayson_read),
};
struct adreno_perfcounters adreno_a630_perfcounters = {
const struct adreno_perfcounters adreno_a630_perfcounters = {
a630_perfcounter_groups,
ARRAY_SIZE(a630_perfcounter_groups),
};
struct adreno_perfcounters adreno_a6xx_perfcounters = {
const struct adreno_perfcounters adreno_a6xx_perfcounters = {
a6xx_perfcounter_groups,
ARRAY_SIZE(a6xx_perfcounter_groups),
};

55
drivers/gpu/msm/adreno_perfcounter.c
View file

@ -67,8 +67,9 @@ static void adreno_perfcounter_write(struct adreno_device *adreno_dev,
*/
void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int counter, groupid;
if (counters == NULL)
@ -100,8 +101,9 @@ void adreno_perfcounter_restore(struct adreno_device *adreno_dev)
*/
inline void adreno_perfcounter_save(struct adreno_device *adreno_dev)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int counter, groupid;
if (counters == NULL)
@ -142,8 +144,9 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
void adreno_perfcounter_start(struct adreno_device *adreno_dev)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int i, j;
if (counters == NULL)
@ -185,8 +188,9 @@ int adreno_perfcounter_read_group(struct adreno_device *adreno_dev,
struct kgsl_perfcounter_read_group __user *reads, unsigned int count)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
struct kgsl_perfcounter_read_group *list = NULL;
unsigned int i, j;
int ret = 0;
@ -266,8 +270,9 @@ done:
int adreno_perfcounter_get_groupid(struct adreno_device *adreno_dev,
const char *name)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
int i;
if (name == NULL || counters == NULL)
@ -300,7 +305,8 @@ int adreno_perfcounter_get_groupid(struct adreno_device *adreno_dev,
const char *adreno_perfcounter_get_name(struct adreno_device *adreno_dev,
unsigned int groupid)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
if (counters != NULL && groupid < counters->group_count)
return counters->groups[groupid].name;
@ -324,8 +330,9 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev,
unsigned int count, unsigned int *max_counters)
{
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int i, t;
int ret = 0;
unsigned int *buf;
@ -370,7 +377,7 @@ int adreno_perfcounter_query_group(struct adreno_device *adreno_dev,
return ret;
}
static inline void refcount_group(struct adreno_perfcount_group *group,
static inline void refcount_group(const struct adreno_perfcount_group *group,
unsigned int reg, unsigned int flags,
unsigned int *lo, unsigned int *hi)
{
@ -404,8 +411,9 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev,
unsigned int groupid, unsigned int countable, unsigned int *offset,
unsigned int *offset_hi, unsigned int flags)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int empty = -1;
int ret = 0;
@ -511,8 +519,9 @@ int adreno_perfcounter_get(struct adreno_device *adreno_dev,
int adreno_perfcounter_put(struct adreno_device *adreno_dev,
unsigned int groupid, unsigned int countable, unsigned int flags)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
unsigned int i;
if (counters == NULL || groupid >= counters->group_count)
@ -563,8 +572,9 @@ int adreno_perfcounter_put(struct adreno_device *adreno_dev,
static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
unsigned int groupid, unsigned int counter, unsigned int countable)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
if (counters == NULL)
return -EINVAL;
@ -592,8 +602,9 @@ static int adreno_perfcounter_enable(struct adreno_device *adreno_dev,
uint64_t adreno_perfcounter_read(struct adreno_device *adreno_dev,
unsigned int groupid, unsigned int counter)
{
struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
/* Lets hope this doesn't fail. Now subfunctions don't need to check */
if (counters == NULL)

12
drivers/gpu/msm/adreno_perfcounter.h
View file

@ -8,8 +8,7 @@
struct adreno_device;
/* ADRENO_PERFCOUNTERS - Given an adreno device, return the perfcounters list */
#define ADRENO_PERFCOUNTERS(_a) \
(ADRENO_GPU_DEVICE(_a) ? ADRENO_GPU_DEVICE(_a)->perfcounters : NULL)
#define ADRENO_PERFCOUNTERS(_a) ((_a)->gpucore->perfcounters)
#define PERFCOUNTER_FLAG_NONE 0x0
#define PERFCOUNTER_FLAG_KERNEL 0x1
@ -49,10 +48,11 @@ struct adreno_perfcount_group {
const char *name;
unsigned long flags;
int (*enable)(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group, unsigned int counter,
unsigned int countable);
const struct adreno_perfcount_group *group,
unsigned int counter, unsigned int countable);
u64 (*read)(struct adreno_device *adreno_dev,
struct adreno_perfcount_group *group, unsigned int counter);
const struct adreno_perfcount_group *group,
unsigned int counter);
};
/*
@ -78,7 +78,7 @@ struct adreno_perfcount_group {
* @group_count: total groups for this device
*/
struct adreno_perfcounters {
struct adreno_perfcount_group *groups;
const struct adreno_perfcount_group *groups;
unsigned int group_count;
};

6
drivers/gpu/msm/adreno_profile.c
View file

@ -954,9 +954,9 @@ static int profile_groups_print(struct seq_file *s, void *unused)
{
struct kgsl_device *device = (struct kgsl_device *) s->private;
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);
struct adreno_perfcounters *counters = gpudev->perfcounters;
struct adreno_perfcount_group *group;
const struct adreno_perfcounters *counters =
ADRENO_PERFCOUNTERS(adreno_dev);
const struct adreno_perfcount_group *group;
int i, j, used;
mutex_lock(&device->mutex);