From fe52ebcd922417ec02b45b88340b20c1b814ca08 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 07:58:12 +0530 Subject: [PATCH 01/11] ARM: dts: msm: Add spss device node for PIL SM8150 Add PIL device tree node to load firmware images of spss on sm8150. Change-Id: I6d4900f815a55f5728fb4d77880007105137b821 --- qcom/sm8150.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index beed59ee7e92..6637792cbc23 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1825,6 +1825,41 @@ mboxes = <&qmp_aop 0>; mbox-names = "slpi-pil"; }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mx-uV = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; }; &firmware { From d04482bb7cb6b85d995f06a93197dcb1baa81918 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:00:58 +0530 Subject: [PATCH 02/11] ARM: dts: msm: Add npu device node for PIL on SM8150 Add PIL device tree node to load firmware images of npu on sm8150. Change-Id: Ief00be65002f90191420b99ae7102897ee565f2b --- qcom/sm8150.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6637792cbc23..5227cbbfb2f7 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1860,6 +1860,17 @@ mboxes = <&qmp_aop 0>; mbox-names = "spss-pil"; }; + + qcom,npu@9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; }; &firmware { From f0b24ffd71bd9da84470633987bfe0d528fa3dac Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:04:22 +0530 Subject: [PATCH 03/11] ARM: dts: msm: Add turing device node for PIL on SM8150 Add PIL device tree node to load firmware images of turing on sm8150. Change-Id: I27ed87d799313ca6732ec71e81e523d9d455762f --- qcom/sm8150.dtsi | 50 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 5227cbbfb2f7..79af9ff97269 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1871,6 +1871,56 @@ memory-region = <&pil_npu_mem>; }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; &firmware { From 3b0b3c18f731a07e90bae0f2bb6e37c68e8ac097 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:08:57 +0530 Subject: [PATCH 04/11] ARM: dts: msm: Add venus device node for PIL on SM8150 Add PIL device tree node to load firmware images of venus on sm8150. Change-Id: I7e9d723823447a3fcb22e93533a448e318d90574 --- qcom/sm8150.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 79af9ff97269..e457858a76e5 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1921,6 +1921,32 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,venus@aae0000 { + compatible = "qcom,pil-tz-generic"; + reg = <0xaae0000 0x4000>; + + vdd-supply = <&mvsc_gdsc>; + qcom,proxy-reg-names = "vdd"; + qcom,complete-ramdump; + + clocks = <&videocc VIDEO_CC_XO_CLK>, + <&videocc VIDEO_CC_MVSC_CORE_CLK>, + <&videocc VIDEO_CC_IRIS_AHB_CLK>; + clock-names = "xo", "core", "ahb"; + qcom,proxy-clock-names = "xo", "core", "ahb"; + + qcom,core-freq = <200000000>; + qcom,ahb-freq = <200000000>; + + qcom,pas-id = <9>; + interconnect-names = "pil-venus"; + interconnects = <&mmss_noc MASTER_VIDEO_P0 + &mc_virt SLAVE_EBI1>; + qcom,proxy-timeout-ms = <100>; + qcom,firmware-name = "venus"; + memory-region = <&pil_video_mem>; + }; }; &firmware { From eeda79ad102c5d6ed7a0c5f676999fd6e6395c26 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 17 Jul 2020 08:14:25 +0530 Subject: [PATCH 05/11] ARM: dts: msm: Enable device nodes for PIL on SM8150 Enable PIL device tree nodes to load firmware images of venus, npu, lpass, spss, on sa8155. Change-Id: I8a5915e57fa208b6bc28475f0d097398f0b6afe5 --- qcom/sa8155-adp-common.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/sa8155-adp-common.dtsi b/qcom/sa8155-adp-common.dtsi index fefcd3bad4be..d7156a1f25f0 100644 --- a/qcom/sa8155-adp-common.dtsi +++ b/qcom/sa8155-adp-common.dtsi @@ -61,3 +61,26 @@ &pil_modem { status = "disabled"; }; + +&soc { + qcom,lpass@17300000 { + status = "ok"; + qcom,pil-force-shutdown; + }; + + qcom,turing@8300000 { + status = "ok"; + }; + + qcom,venus@aae0000 { + status = "ok"; + }; + + qcom,spss@1880000 { + status = "ok"; + }; + + qcom,npu@9800000 { + status = "ok"; + }; +}; From 94be92caece46ebb7eb67c25e50dc80475109546 Mon Sep 17 00:00:00 2001 From: Yadu MG Date: Wed, 29 Jul 2020 11:56:51 +0530 Subject: [PATCH 06/11] ARM: dts: msm: Fix wdog interrupts on pil subsystems for SM8150 On newer kernels PDC interrupt can only be requested if its actually routed through PDC HW. Update the pil subsystems interrupts to use intc interrupts when they are direct interrupts at GIC and only use PDC if it has routing to PDC HW. Also, add missing properties vdd_mx-supply and shutdown-ack to pil lpass node. Change-Id: Ie60515cd51e55ce0772d5d2c89a603b63ba44545 --- qcom/sm8150.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index e457858a76e5..2825173ad88c 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1712,7 +1712,7 @@ qcom,complete-ramdump; /* Inputs from mss */ - interrupts-extended = <&pdc 0 266 1>, + interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, <&modem_smp2p_in 2 0>, <&modem_smp2p_in 1 0>, @@ -1740,7 +1740,9 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; qcom,vdd_cx-uV-uA = ; - qcom,proxy-reg-names = "vdd_cx"; + vdd_mx-supply = <&VDD_MX_LEVEL>; + qcom,vdd_mx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx","vdd_mx"; clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; @@ -1755,20 +1757,21 @@ memory-region = <&pil_adsp_mem>; qcom,signal-aop; qcom,complete-ramdump; - qcom,pil-force-shutdown; /* Inputs from lpass */ - interrupts-extended = <&pdc 0 162 1>, + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", - "qcom,stop-ack"; + "qcom,stop-ack", + "qcom,shutdown-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -1806,7 +1809,7 @@ qcom,complete-ramdump; /* Inputs from ssc */ - interrupts-extended = <&pdc 0 494 1>, + interrupts-extended = <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, <&dsps_smp2p_in 0 0>, <&dsps_smp2p_in 2 0>, <&dsps_smp2p_in 1 0>, From 4e5cad47bf9554ef9970208c832c8095bdfdf896 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:07:31 +0530 Subject: [PATCH 07/11] ARM: dts: msm: Add scm & scm-pas device on SDMSHRIKE Add device nodes for scm & scm-pas for SDMSHRIKE SoC. This is needed to secure memory buffers, and protect them against unauthorized access. Change-Id: Ia7d57cd3b2ef520839d46a77da64fd0aa2ca1d6a --- qcom/sdmshrike.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 006a1d4bb2a2..f3ba2a28e8b3 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -503,6 +503,10 @@ compatible = "simple-bus"; }; + qcom-secure-buffer { + compatible = "qcom,secure-buffer"; + }; + soc: soc { }; }; @@ -665,6 +669,12 @@ qcom,rtb-size = <0x100000>; }; + pil_scm_pas { + compatible = "qcom,pil-tz-scm-pas"; + interconnects = <&aggre2_noc MASTER_CRYPTO + &mc_virt SLAVE_EBI1>; + }; + qcom,mpm2-sleep-counter@c221000 { compatible = "qcom,mpm2-sleep-counter"; reg = <0xc221000 0x1000>; @@ -1481,6 +1491,12 @@ #include "sa8195-ssc-qupv3.dtsi" #include "sa8195-usb.dtsi" +&firmware { + scm { + compatible = "qcom,scm"; + }; +}; + &emac_gdsc { status = "ok"; }; From e71c756ffc0f6acb84912717fe2ce77abf81e9d7 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:45:45 +0530 Subject: [PATCH 08/11] ARM: dts: msm: Add lpass device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of lpass on SDMSHRIKE. Change-Id: Ic04366af333b8cb9292820539937df1d538c769d --- qcom/sdmshrike.dtsi | 44 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index f3ba2a28e8b3..9ea6492e327f 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1463,7 +1463,6 @@ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; qcom,devfreq,freq-table = <50000000 200000000>; - status = "disabled"; qos0 { @@ -1477,6 +1476,49 @@ }; }; + qcom,lpass@17300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x17300000 0x00100>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <1>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <423>; + qcom,sysmon-id = <1>; + qcom,ssctl-instance-id = <0x14>; + qcom,firmware-name = "adsp"; + memory-region = <&pil_adsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + qcom,pil-force-shutdown; + + /* Inputs from lpass */ + interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&adsp_smp2p_in 0 0>, + <&adsp_smp2p_in 2 0>, + <&adsp_smp2p_in 1 0>, + <&adsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to lpass */ + qcom,smem-states = <&adsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "adsp-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi" From e4a8c511b36accc01b88d42298a1aeccb2ed98d1 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Wed, 19 Aug 2020 22:53:23 +0530 Subject: [PATCH 09/11] ARM: dts: msm: Add turing device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware image of turing on SDMSHRIKE. Change-Id: I1b3baa6587f738be5e7f7112c35a082bb6c2f317 --- qcom/sdmshrike.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 9ea6492e327f..c41aace55b9c 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1519,6 +1519,56 @@ mboxes = <&qmp_aop 0>; mbox-names = "adsp-pil"; }; + + qcom,turing@8300000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x8300000 0x100000>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + qcom,pas-id = <18>; + qcom,proxy-timeout-ms = <10000>; + qcom,smem-id = <601>; + qcom,sysmon-id = <7>; + qcom,ssctl-instance-id = <0x17>; + qcom,firmware-name = "cdsp"; + memory-region = <&pil_cdsp_mem>; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,msm-bus,name = "pil-cdsp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <154 10070 0 0>, + <154 10070 0 1>; + + /* Inputs from turing */ + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, + <&cdsp_smp2p_in 0 0>, + <&cdsp_smp2p_in 2 0>, + <&cdsp_smp2p_in 1 0>, + <&cdsp_smp2p_in 3 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack"; + + /* Outputs to turing */ + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + mboxes = <&qmp_aop 0>; + mbox-names = "cdsp-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi" From 6b11e0a44a647261d8ae2135591dbf24a2c889a6 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 14 Aug 2020 14:38:58 +0530 Subject: [PATCH 10/11] ARM: dts: msm: Add npu device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of npu on SDMSHRIKE. Change-Id: I8ec1d063fc79aad4759c573dca6fe8e933a109c2 --- qcom/sdmshrike.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index c41aace55b9c..35ea04de2ac4 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1569,6 +1569,17 @@ mboxes = <&qmp_aop 0>; mbox-names = "cdsp-pil"; }; + + qcom,npu@9800000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x9800000 0x800000>; + + status = "ok"; + qcom,pas-id = <23>; + qcom,firmware-name = "npu"; + + memory-region = <&pil_npu_mem>; + }; }; #include "sdmshrike-pinctrl.dtsi" From bf71e319b638cc21aa7018e0dfb3b76214b88807 Mon Sep 17 00:00:00 2001 From: Saurabh Ambulkar Date: Fri, 14 Aug 2020 14:51:03 +0530 Subject: [PATCH 11/11] ARM: dts: msm: Add spss device node for PIL on SDMSHRIKE Add PIL device tree node to load firmware images of spss on SDMSHRIKE. Change-Id: I61acf03594390dbcdb47f38443b32969f10e9542 --- qcom/sdmshrike.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 35ea04de2ac4..51d4254d722b 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1580,6 +1580,41 @@ memory-region = <&pil_npu_mem>; }; + + qcom,spss@1880000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,proxy-reg-names = "vdd_cx"; + qcom,vdd_cx-uV-uA = ; + vdd_mx-supply = <&VDD_MX_LEVEL>; + vdd_mx-uV = ; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + qcom,pil-generic-irq-handler; + status = "ok"; + qcom,signal-aop; + qcom,complete-ramdump; + + qcom,pas-id = <14>; + qcom,proxy-timeout-ms = <10000>; + qcom,firmware-name = "spss"; + memory-region = <&pil_spss_mem>; + qcom,spss-scsr-bits = <24 25>; + + mboxes = <&qmp_aop 0>; + mbox-names = "spss-pil"; + }; }; #include "sdmshrike-pinctrl.dtsi"