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ARM: dts: msm: clean up cache-size properties

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d-cache-size/i-cache-size/cache-size properties
of caches are not required for any functionality,
so remove these redundant entries from device tree.

Change-Id: Ie2091a210d088215780343f13a4e918047d5a14f
This commit is contained in:
Kaushal Kumar 2020-04-25 21:25:00 +05:30
commit bab2202031
4 changed files with 0 additions and 76 deletions
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17
qcom/holi.dtsi
View file

@ -23,18 +23,15 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x100000>;
cache-level = <3>;
};
};
@ -45,12 +42,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -61,12 +56,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -77,12 +70,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -93,12 +84,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -109,12 +98,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x10000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -125,12 +112,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cache-size = <0x10000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -141,12 +126,10 @@
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cache-size = <0x10000>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};

17
qcom/lahaina.dtsi
View file

@ -66,7 +66,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
@ -76,13 +75,11 @@
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x200000>;
cache-level = <3>;
};
};
@ -93,7 +90,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
@ -103,7 +99,6 @@
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -114,7 +109,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
@ -124,7 +118,6 @@
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -135,7 +128,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
@ -145,7 +137,6 @@
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -156,7 +147,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
@ -166,7 +156,6 @@
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -177,7 +166,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
@ -187,7 +175,6 @@
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -198,7 +185,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
@ -208,7 +194,6 @@
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -219,7 +204,6 @@
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
capacity-dmips-mhz = <2048>;
@ -229,7 +213,6 @@
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};

25
qcom/shima.dtsi
View file

@ -36,19 +36,15 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x200000>;
cache-level = <3>;
};
};
@ -61,13 +57,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -80,13 +73,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -99,13 +89,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -118,13 +105,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -137,13 +121,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -156,13 +137,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -175,13 +153,10 @@
enable-method = "psci";
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <552>;
d-cache-size = <0x8000>;
i-cache-size = <0x8000>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};

17
qcom/sm8150.dtsi
View file

@ -28,17 +28,14 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-size = <0x200000>;
cache-level = <3>;
};
};
@ -65,11 +62,9 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -96,11 +91,9 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -127,11 +120,9 @@
enable-method = "psci";
cpu-idle-states = <&SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
cache-size = <0x8000>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x20000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
};
@ -158,11 +149,9 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@ -198,11 +187,9 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@ -238,11 +225,9 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x40000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x88000>;
@ -278,11 +263,9 @@
enable-method = "psci";
cpu-idle-states = <&GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1740>;
cache-size = <0x20000>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-size = <0x80000>;
cache-level = <2>;
next-level-cache = <&L3_0>;
qcom,dump-size = <0x110000>;