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Merge ../linux-2.6

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This commit is contained in:
Paul Mackerras 2006-03-29 13:24:50 +11:00
commit bac30d1a78
779 changed files with 22983 additions and 7760 deletions
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27
drivers/video/Kconfig
View file

@ -70,6 +70,22 @@ config FB_MACMODES
depends on FB
default n
config FB_FIRMWARE_EDID
bool "Enable firmware EDID"
depends on FB
default y
---help---
This enables access to the EDID transferred from the firmware.
On the i386, this is from the Video BIOS. Enable this if DDC/I2C
transfers do not work for your driver and if you are using
nvidiafb, i810fb or savagefb.
In general, choosing Y for this option is safe. If you
experience extremely long delays while booting before you get
something on your display, try setting this to N. Matrox cards in
combination with certain motherboards and monitors are known to
suffer from this problem.
config FB_MODE_HELPERS
bool "Enable Video Mode Handling Helpers"
depends on FB
@ -1202,6 +1218,17 @@ config FB_AU1100
bool "Au1100 LCD Driver"
depends on (FB = y) && EXPERIMENTAL && PCI && MIPS && MIPS_PB1100=y
config FB_AU1200
bool "Au1200 LCD Driver"
depends on FB && MIPS && SOC_AU1200
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
This is the framebuffer driver for the AMD Au1200 SOC. It can drive
various panels and CRTs by passing in kernel cmd line option
au1200fb:panel=<name>.
source "drivers/video/geode/Kconfig"
config FB_FFB

1
drivers/video/Makefile
View file

@ -86,6 +86,7 @@ obj-$(CONFIG_FB_ASILIANT) += asiliantfb.o
obj-$(CONFIG_FB_PXA) += pxafb.o
obj-$(CONFIG_FB_W100) += w100fb.o
obj-$(CONFIG_FB_AU1100) += au1100fb.o
obj-$(CONFIG_FB_AU1200) += au1200fb.o
obj-$(CONFIG_FB_PMAG_AA) += pmag-aa-fb.o
obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o
obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o

8
drivers/video/acornfb.c
View file

@ -1308,7 +1308,7 @@ static int __init acornfb_probe(struct platform_device *dev)
/*
* Try to select a suitable default mode
*/
for (i = 0; i < sizeof(modedb) / sizeof(*modedb); i++) {
for (i = 0; i < ARRAY_SIZE(modedb); i++) {
unsigned long hs;
hs = modedb[i].refresh *
@ -1380,7 +1380,7 @@ static int __init acornfb_probe(struct platform_device *dev)
*/
free_unused_pages(PAGE_OFFSET + size, PAGE_OFFSET + MAX_SIZE);
#endif
fb_info.fix.smem_len = size;
current_par.palette_size = VIDC_PALETTE_SIZE;
@ -1391,7 +1391,7 @@ static int __init acornfb_probe(struct platform_device *dev)
*/
do {
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
sizeof(modedb) / sizeof(*modedb),
ARRAY_SIZE(modedb),
&acornfb_default_mode, DEFAULT_BPP);
/*
* If we found an exact match, all ok.
@ -1408,7 +1408,7 @@ static int __init acornfb_probe(struct platform_device *dev)
break;
rc = fb_find_mode(&fb_info.var, &fb_info, NULL, modedb,
sizeof(modedb) / sizeof(*modedb),
ARRAY_SIZE(modedb),
&acornfb_default_mode, DEFAULT_BPP);
if (rc)
break;

14
drivers/video/asiliantfb.c
View file

@ -353,8 +353,6 @@ struct chips_init_reg {
unsigned char data;
};
#define N_ELTS(x) (sizeof(x) / sizeof(x[0]))
static struct chips_init_reg chips_init_sr[] =
{
{0x00, 0x03}, /* Reset register */
@ -460,22 +458,22 @@ static void __devinit chips_hw_init(struct fb_info *p)
{
int i;
for (i = 0; i < N_ELTS(chips_init_xr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
write_xr(0x81, 0x12);
write_xr(0x82, 0x08);
write_xr(0x20, 0x00);
for (i = 0; i < N_ELTS(chips_init_sr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
for (i = 0; i < N_ELTS(chips_init_gr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
for (i = 0; i < N_ELTS(chips_init_ar); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
/* Enable video output in attribute index register */
writeb(0x20, mmio_base + 0x780);
for (i = 0; i < N_ELTS(chips_init_cr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
for (i = 0; i < N_ELTS(chips_init_fr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
}

4
drivers/video/aty/aty128fb.c
View file

@ -1726,9 +1726,9 @@ static int __init aty128_init(struct pci_dev *pdev, const struct pci_device_id *
strcpy(video_card, "Rage128 XX ");
video_card[8] = ent->device >> 8;
video_card[9] = ent->device & 0xFF;
/* range check to make sure */
if (ent->driver_data < (sizeof(r128_family)/sizeof(char *)))
if (ent->driver_data < ARRAY_SIZE(r128_family))
strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);

16
drivers/video/aty/atyfb_base.c
View file

@ -435,7 +435,7 @@ static int __devinit correct_chipset(struct atyfb_par *par)
const char *name;
int i;
for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
if (par->pci_id == aty_chips[i].pci_id)
break;
@ -2169,10 +2169,10 @@ static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
refresh_tbl = ragexl_tbl;
size = sizeof(ragexl_tbl)/sizeof(int);
size = ARRAY_SIZE(ragexl_tbl);
} else {
refresh_tbl = ragepro_tbl;
size = sizeof(ragepro_tbl)/sizeof(int);
size = ARRAY_SIZE(ragepro_tbl);
}
for (i=0; i < size; i++) {
@ -2299,6 +2299,10 @@ static int __init aty_init(struct fb_info *info, const char *name)
case CLK_ATI18818_1:
par->pll_ops = &aty_pll_ati18818_1;
break;
case CLK_IBMRGB514:
par->pll_ops = &aty_pll_ibm514;
break;
#if 0 /* dead code */
case CLK_STG1703:
par->pll_ops = &aty_pll_stg1703;
break;
@ -2308,9 +2312,7 @@ static int __init aty_init(struct fb_info *info, const char *name)
case CLK_ATT20C408:
par->pll_ops = &aty_pll_att20c408;
break;
case CLK_IBMRGB514:
par->pll_ops = &aty_pll_ibm514;
break;
#endif
default:
PRINTKI("aty_init: CLK type not implemented yet!");
par->pll_ops = &aty_pll_unsupported;
@ -3398,7 +3400,7 @@ static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_devi
struct atyfb_par *par;
int i, rc = -ENOMEM;
for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
for (i = ARRAY_SIZE(aty_chips); i >= 0; i--)
if (pdev->device == aty_chips[i].pci_id)
break;

3
drivers/video/aty/mach64_gx.c
View file

@ -149,8 +149,7 @@ static int aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per,
};
int i;
for (i = 0; i < sizeof(RGB514_clocks) / sizeof(*RGB514_clocks);
i++)
for (i = 0; i < ARRAY_SIZE(RGB514_clocks); i++)
if (vclk_per <= RGB514_clocks[i].limit) {
pll->ibm514.m = RGB514_clocks[i].m;
pll->ibm514.n = RGB514_clocks[i].n;

6
drivers/video/aty/radeon_base.c
View file

@ -1067,7 +1067,7 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
if (regno > 255)
return 1;
return -EINVAL;
red >>= 8;
green >>= 8;
@ -1086,9 +1086,9 @@ static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
pindex = regno * 8;
if (rinfo->depth == 16 && regno > 63)
return 1;
return -EINVAL;
if (rinfo->depth == 15 && regno > 31)
return 1;
return -EINVAL;
/* For 565, the green component is mixed one order
* below

3844
drivers/video/au1200fb.c Normal file
View file

File diff suppressed because it is too large Load diff

572
drivers/video/au1200fb.h Normal file
View file

@ -0,0 +1,572 @@
/*
* BRIEF MODULE DESCRIPTION
* Hardware definitions for the Au1200 LCD controller
*
* Copyright 2004 AMD
* Author: AMD
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _AU1200LCD_H
#define _AU1200LCD_H
/********************************************************************/
#define AU1200_LCD_ADDR 0xB5000000
#define uint8 unsigned char
#define uint32 unsigned int
struct au1200_lcd {
volatile uint32 reserved0;
volatile uint32 screen;
volatile uint32 backcolor;
volatile uint32 horztiming;
volatile uint32 verttiming;
volatile uint32 clkcontrol;
volatile uint32 pwmdiv;
volatile uint32 pwmhi;
volatile uint32 reserved1;
volatile uint32 winenable;
volatile uint32 colorkey;
volatile uint32 colorkeymsk;
struct
{
volatile uint32 cursorctrl;
volatile uint32 cursorpos;
volatile uint32 cursorcolor0;
volatile uint32 cursorcolor1;
volatile uint32 cursorcolor2;
uint32 cursorcolor3;
} hwc;
volatile uint32 intstatus;
volatile uint32 intenable;
volatile uint32 outmask;
volatile uint32 fifoctrl;
uint32 reserved2[(0x0100-0x0058)/4];
struct
{
volatile uint32 winctrl0;
volatile uint32 winctrl1;
volatile uint32 winctrl2;
volatile uint32 winbuf0;
volatile uint32 winbuf1;
volatile uint32 winbufctrl;
uint32 winreserved0;
uint32 winreserved1;
} window[4];
uint32 reserved3[(0x0400-0x0180)/4];
volatile uint32 palette[(0x0800-0x0400)/4];
volatile uint8 cursorpattern[256];
};
/* lcd_screen */
#define LCD_SCREEN_SEN (1<<31)
#define LCD_SCREEN_SX (0x07FF<<19)
#define LCD_SCREEN_SY (0x07FF<< 8)
#define LCD_SCREEN_SWP (1<<7)
#define LCD_SCREEN_SWD (1<<6)
#define LCD_SCREEN_PT (7<<0)
#define LCD_SCREEN_PT_TFT (0<<0)
#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
#define LCD_SCREEN_PT_CSTN (1<<0)
#define LCD_SCREEN_PT_CDSTN (2<<0)
#define LCD_SCREEN_PT_M8STN (3<<0)
#define LCD_SCREEN_PT_M4STN (4<<0)
/* lcd_backcolor */
#define LCD_BACKCOLOR_SBGR (0xFF<<16)
#define LCD_BACKCOLOR_SBGG (0xFF<<8)
#define LCD_BACKCOLOR_SBGB (0xFF<<0)
#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16)
#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8)
#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0)
/* lcd_winenable */
#define LCD_WINENABLE_WEN3 (1<<3)
#define LCD_WINENABLE_WEN2 (1<<2)
#define LCD_WINENABLE_WEN1 (1<<1)
#define LCD_WINENABLE_WEN0 (1<<0)
/* lcd_colorkey */
#define LCD_COLORKEY_CKR (0xFF<<16)
#define LCD_COLORKEY_CKG (0xFF<<8)
#define LCD_COLORKEY_CKB (0xFF<<0)
#define LCD_COLORKEY_CKR_N(N) ((N)<<16)
#define LCD_COLORKEY_CKG_N(N) ((N)<<8)
#define LCD_COLORKEY_CKB_N(N) ((N)<<0)
/* lcd_colorkeymsk */
#define LCD_COLORKEYMSK_CKMR (0xFF<<16)
#define LCD_COLORKEYMSK_CKMG (0xFF<<8)
#define LCD_COLORKEYMSK_CKMB (0xFF<<0)
#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16)
#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8)
#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0)
/* lcd windows control 0 */
#define LCD_WINCTRL0_OX (0x07FF<<21)
#define LCD_WINCTRL0_OY (0x07FF<<10)
#define LCD_WINCTRL0_A (0x00FF<<2)
#define LCD_WINCTRL0_AEN (1<<1)
#define LCD_WINCTRL0_OX_N(N) ((N)<<21)
#define LCD_WINCTRL0_OY_N(N) ((N)<<10)
#define LCD_WINCTRL0_A_N(N) ((N)<<2)
/* lcd windows control 1 */
#define LCD_WINCTRL1_PRI (3<<30)
#define LCD_WINCTRL1_PIPE (1<<29)
#define LCD_WINCTRL1_FRM (0xF<<25)
#define LCD_WINCTRL1_CCO (1<<24)
#define LCD_WINCTRL1_PO (3<<22)
#define LCD_WINCTRL1_SZX (0x07FF<<11)
#define LCD_WINCTRL1_SZY (0x07FF<<0)
#define LCD_WINCTRL1_FRM_1BPP (0<<25)
#define LCD_WINCTRL1_FRM_2BPP (1<<25)
#define LCD_WINCTRL1_FRM_4BPP (2<<25)
#define LCD_WINCTRL1_FRM_8BPP (3<<25)
#define LCD_WINCTRL1_FRM_12BPP (4<<25)
#define LCD_WINCTRL1_FRM_16BPP655 (5<<25)
#define LCD_WINCTRL1_FRM_16BPP565 (6<<25)
#define LCD_WINCTRL1_FRM_16BPP556 (7<<25)
#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25)
#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25)
#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25)
#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25)
#define LCD_WINCTRL1_FRM_24BPP (12<<25)
#define LCD_WINCTRL1_FRM_32BPP (13<<25)
#define LCD_WINCTRL1_PRI_N(N) ((N)<<30)
#define LCD_WINCTRL1_PO_00 (0<<22)
#define LCD_WINCTRL1_PO_01 (1<<22)
#define LCD_WINCTRL1_PO_10 (2<<22)
#define LCD_WINCTRL1_PO_11 (3<<22)
#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11)
#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0)
/* lcd windows control 2 */
#define LCD_WINCTRL2_CKMODE (3<<24)
#define LCD_WINCTRL2_DBM (1<<23)
#define LCD_WINCTRL2_RAM (3<<21)
#define LCD_WINCTRL2_BX (0x1FFF<<8)
#define LCD_WINCTRL2_SCX (0xF<<4)
#define LCD_WINCTRL2_SCY (0xF<<0)
#define LCD_WINCTRL2_CKMODE_00 (0<<24)
#define LCD_WINCTRL2_CKMODE_01 (1<<24)
#define LCD_WINCTRL2_CKMODE_10 (2<<24)
#define LCD_WINCTRL2_CKMODE_11 (3<<24)
#define LCD_WINCTRL2_RAM_NONE (0<<21)
#define LCD_WINCTRL2_RAM_PALETTE (1<<21)
#define LCD_WINCTRL2_RAM_GAMMA (2<<21)
#define LCD_WINCTRL2_RAM_BUFFER (3<<21)
#define LCD_WINCTRL2_BX_N(N) ((N)<<8)
#define LCD_WINCTRL2_SCX_1 (0<<4)
#define LCD_WINCTRL2_SCX_2 (1<<4)
#define LCD_WINCTRL2_SCX_4 (2<<4)
#define LCD_WINCTRL2_SCY_1 (0<<0)
#define LCD_WINCTRL2_SCY_2 (1<<0)
#define LCD_WINCTRL2_SCY_4 (2<<0)
/* lcd windows buffer control */
#define LCD_WINBUFCTRL_DB (1<<1)
#define LCD_WINBUFCTRL_DBN (1<<0)
/* lcd_intstatus, lcd_intenable */
#define LCD_INT_IFO (0xF<<14)
#define LCD_INT_IFU (0xF<<10)
#define LCD_INT_OFO (1<<9)
#define LCD_INT_OFU (1<<8)
#define LCD_INT_WAIT (1<<3)
#define LCD_INT_SD (1<<2)
#define LCD_INT_SA (1<<1)
#define LCD_INT_SS (1<<0)
/* lcd_horztiming */
#define LCD_HORZTIMING_HND2 (0x1FF<<18)
#define LCD_HORZTIMING_HND1 (0x1FF<<9)
#define LCD_HORZTIMING_HPW (0x1FF<<0)
#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0)
/* lcd_verttiming */
#define LCD_VERTTIMING_VND2 (0x1FF<<18)
#define LCD_VERTTIMING_VND1 (0x1FF<<9)
#define LCD_VERTTIMING_VPW (0x1FF<<0)
#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0)
/* lcd_clkcontrol */
#define LCD_CLKCONTROL_EXT (1<<22)
#define LCD_CLKCONTROL_DELAY (3<<20)
#define LCD_CLKCONTROL_CDD (1<<19)
#define LCD_CLKCONTROL_IB (1<<18)
#define LCD_CLKCONTROL_IC (1<<17)
#define LCD_CLKCONTROL_IH (1<<16)
#define LCD_CLKCONTROL_IV (1<<15)
#define LCD_CLKCONTROL_BF (0x1F<<10)
#define LCD_CLKCONTROL_PCD (0x3FF<<0)
#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
/* lcd_pwmdiv */
#define LCD_PWMDIV_EN (1<<31)
#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0)
#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0)
/* lcd_pwmhi */
#define LCD_PWMHI_PWMHI1 (0xFFFF<<16)
#define LCD_PWMHI_PWMHI0 (0xFFFF<<0)
#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16)
#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
/* lcd_hwccon */
#define LCD_HWCCON_EN (1<<0)
/* lcd_cursorpos */
#define LCD_CURSORPOS_HWCXOFF (0x1F<<27)
#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16)
#define LCD_CURSORPOS_HWCYOFF (0x1F<<11)
#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0)
#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27)
#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16)
#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11)
#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0)
/* lcd_cursorcolor */
#define LCD_CURSORCOLOR_HWCA (0xFF<<24)
#define LCD_CURSORCOLOR_HWCR (0xFF<<16)
#define LCD_CURSORCOLOR_HWCG (0xFF<<8)
#define LCD_CURSORCOLOR_HWCB (0xFF<<0)
#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24)
#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16)
#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8)
#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0)
/* lcd_fifoctrl */
#define LCD_FIFOCTRL_F3IF (1<<29)
#define LCD_FIFOCTRL_F3REQ (0x1F<<24)
#define LCD_FIFOCTRL_F2IF (1<<29)
#define LCD_FIFOCTRL_F2REQ (0x1F<<16)
#define LCD_FIFOCTRL_F1IF (1<<29)
#define LCD_FIFOCTRL_F1REQ (0x1F<<8)
#define LCD_FIFOCTRL_F0IF (1<<29)
#define LCD_FIFOCTRL_F0REQ (0x1F<<0)
#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24)
#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16)
#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8)
#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0)
/* lcd_outmask */
#define LCD_OUTMASK_MASK (0x00FFFFFF)
/********************************************************************/
#endif /* _AU1200LCD_H */
/*
* BRIEF MODULE DESCRIPTION
* Hardware definitions for the Au1200 LCD controller
*
* Copyright 2004 AMD
* Author: AMD
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _AU1200LCD_H
#define _AU1200LCD_H
/********************************************************************/
#define AU1200_LCD_ADDR 0xB5000000
#define uint8 unsigned char
#define uint32 unsigned int
struct au1200_lcd {
volatile uint32 reserved0;
volatile uint32 screen;
volatile uint32 backcolor;
volatile uint32 horztiming;
volatile uint32 verttiming;
volatile uint32 clkcontrol;
volatile uint32 pwmdiv;
volatile uint32 pwmhi;
volatile uint32 reserved1;
volatile uint32 winenable;
volatile uint32 colorkey;
volatile uint32 colorkeymsk;
struct
{
volatile uint32 cursorctrl;
volatile uint32 cursorpos;
volatile uint32 cursorcolor0;
volatile uint32 cursorcolor1;
volatile uint32 cursorcolor2;
uint32 cursorcolor3;
} hwc;
volatile uint32 intstatus;
volatile uint32 intenable;
volatile uint32 outmask;
volatile uint32 fifoctrl;
uint32 reserved2[(0x0100-0x0058)/4];
struct
{
volatile uint32 winctrl0;
volatile uint32 winctrl1;
volatile uint32 winctrl2;
volatile uint32 winbuf0;
volatile uint32 winbuf1;
volatile uint32 winbufctrl;
uint32 winreserved0;
uint32 winreserved1;
} window[4];
uint32 reserved3[(0x0400-0x0180)/4];
volatile uint32 palette[(0x0800-0x0400)/4];
volatile uint8 cursorpattern[256];
};
/* lcd_screen */
#define LCD_SCREEN_SEN (1<<31)
#define LCD_SCREEN_SX (0x07FF<<19)
#define LCD_SCREEN_SY (0x07FF<< 8)
#define LCD_SCREEN_SWP (1<<7)
#define LCD_SCREEN_SWD (1<<6)
#define LCD_SCREEN_PT (7<<0)
#define LCD_SCREEN_PT_TFT (0<<0)
#define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
#define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
#define LCD_SCREEN_PT_CSTN (1<<0)
#define LCD_SCREEN_PT_CDSTN (2<<0)
#define LCD_SCREEN_PT_M8STN (3<<0)
#define LCD_SCREEN_PT_M4STN (4<<0)
/* lcd_backcolor */
#define LCD_BACKCOLOR_SBGR (0xFF<<16)
#define LCD_BACKCOLOR_SBGG (0xFF<<8)
#define LCD_BACKCOLOR_SBGB (0xFF<<0)
#define LCD_BACKCOLOR_SBGR_N(N) ((N)<<16)
#define LCD_BACKCOLOR_SBGG_N(N) ((N)<<8)
#define LCD_BACKCOLOR_SBGB_N(N) ((N)<<0)
/* lcd_winenable */
#define LCD_WINENABLE_WEN3 (1<<3)
#define LCD_WINENABLE_WEN2 (1<<2)
#define LCD_WINENABLE_WEN1 (1<<1)
#define LCD_WINENABLE_WEN0 (1<<0)
/* lcd_colorkey */
#define LCD_COLORKEY_CKR (0xFF<<16)
#define LCD_COLORKEY_CKG (0xFF<<8)
#define LCD_COLORKEY_CKB (0xFF<<0)
#define LCD_COLORKEY_CKR_N(N) ((N)<<16)
#define LCD_COLORKEY_CKG_N(N) ((N)<<8)
#define LCD_COLORKEY_CKB_N(N) ((N)<<0)
/* lcd_colorkeymsk */
#define LCD_COLORKEYMSK_CKMR (0xFF<<16)
#define LCD_COLORKEYMSK_CKMG (0xFF<<8)
#define LCD_COLORKEYMSK_CKMB (0xFF<<0)
#define LCD_COLORKEYMSK_CKMR_N(N) ((N)<<16)
#define LCD_COLORKEYMSK_CKMG_N(N) ((N)<<8)
#define LCD_COLORKEYMSK_CKMB_N(N) ((N)<<0)
/* lcd windows control 0 */
#define LCD_WINCTRL0_OX (0x07FF<<21)
#define LCD_WINCTRL0_OY (0x07FF<<10)
#define LCD_WINCTRL0_A (0x00FF<<2)
#define LCD_WINCTRL0_AEN (1<<1)
#define LCD_WINCTRL0_OX_N(N) ((N)<<21)
#define LCD_WINCTRL0_OY_N(N) ((N)<<10)
#define LCD_WINCTRL0_A_N(N) ((N)<<2)
/* lcd windows control 1 */
#define LCD_WINCTRL1_PRI (3<<30)
#define LCD_WINCTRL1_PIPE (1<<29)
#define LCD_WINCTRL1_FRM (0xF<<25)
#define LCD_WINCTRL1_CCO (1<<24)
#define LCD_WINCTRL1_PO (3<<22)
#define LCD_WINCTRL1_SZX (0x07FF<<11)
#define LCD_WINCTRL1_SZY (0x07FF<<0)
#define LCD_WINCTRL1_FRM_1BPP (0<<25)
#define LCD_WINCTRL1_FRM_2BPP (1<<25)
#define LCD_WINCTRL1_FRM_4BPP (2<<25)
#define LCD_WINCTRL1_FRM_8BPP (3<<25)
#define LCD_WINCTRL1_FRM_12BPP (4<<25)
#define LCD_WINCTRL1_FRM_16BPP655 (5<<25)
#define LCD_WINCTRL1_FRM_16BPP565 (6<<25)
#define LCD_WINCTRL1_FRM_16BPP556 (7<<25)
#define LCD_WINCTRL1_FRM_16BPPI1555 (8<<25)
#define LCD_WINCTRL1_FRM_16BPPI5551 (9<<25)
#define LCD_WINCTRL1_FRM_16BPPA1555 (10<<25)
#define LCD_WINCTRL1_FRM_16BPPA5551 (11<<25)
#define LCD_WINCTRL1_FRM_24BPP (12<<25)
#define LCD_WINCTRL1_FRM_32BPP (13<<25)
#define LCD_WINCTRL1_PRI_N(N) ((N)<<30)
#define LCD_WINCTRL1_PO_00 (0<<22)
#define LCD_WINCTRL1_PO_01 (1<<22)
#define LCD_WINCTRL1_PO_10 (2<<22)
#define LCD_WINCTRL1_PO_11 (3<<22)
#define LCD_WINCTRL1_SZX_N(N) ((N-1)<<11)
#define LCD_WINCTRL1_SZY_N(N) ((N-1)<<0)
/* lcd windows control 2 */
#define LCD_WINCTRL2_CKMODE (3<<24)
#define LCD_WINCTRL2_DBM (1<<23)
#define LCD_WINCTRL2_RAM (3<<21)
#define LCD_WINCTRL2_BX (0x1FFF<<8)
#define LCD_WINCTRL2_SCX (0xF<<4)
#define LCD_WINCTRL2_SCY (0xF<<0)
#define LCD_WINCTRL2_CKMODE_00 (0<<24)
#define LCD_WINCTRL2_CKMODE_01 (1<<24)
#define LCD_WINCTRL2_CKMODE_10 (2<<24)
#define LCD_WINCTRL2_CKMODE_11 (3<<24)
#define LCD_WINCTRL2_RAM_NONE (0<<21)
#define LCD_WINCTRL2_RAM_PALETTE (1<<21)
#define LCD_WINCTRL2_RAM_GAMMA (2<<21)
#define LCD_WINCTRL2_RAM_BUFFER (3<<21)
#define LCD_WINCTRL2_BX_N(N) ((N)<<8)
#define LCD_WINCTRL2_SCX_1 (0<<4)
#define LCD_WINCTRL2_SCX_2 (1<<4)
#define LCD_WINCTRL2_SCX_4 (2<<4)
#define LCD_WINCTRL2_SCY_1 (0<<0)
#define LCD_WINCTRL2_SCY_2 (1<<0)
#define LCD_WINCTRL2_SCY_4 (2<<0)
/* lcd windows buffer control */
#define LCD_WINBUFCTRL_DB (1<<1)
#define LCD_WINBUFCTRL_DBN (1<<0)
/* lcd_intstatus, lcd_intenable */
#define LCD_INT_IFO (0xF<<14)
#define LCD_INT_IFU (0xF<<10)
#define LCD_INT_OFO (1<<9)
#define LCD_INT_OFU (1<<8)
#define LCD_INT_WAIT (1<<3)
#define LCD_INT_SD (1<<2)
#define LCD_INT_SA (1<<1)
#define LCD_INT_SS (1<<0)
/* lcd_horztiming */
#define LCD_HORZTIMING_HND2 (0x1FF<<18)
#define LCD_HORZTIMING_HND1 (0x1FF<<9)
#define LCD_HORZTIMING_HPW (0x1FF<<0)
#define LCD_HORZTIMING_HND2_N(N)(((N)-1)<<18)
#define LCD_HORZTIMING_HND1_N(N)(((N)-1)<<9)
#define LCD_HORZTIMING_HPW_N(N) (((N)-1)<<0)
/* lcd_verttiming */
#define LCD_VERTTIMING_VND2 (0x1FF<<18)
#define LCD_VERTTIMING_VND1 (0x1FF<<9)
#define LCD_VERTTIMING_VPW (0x1FF<<0)
#define LCD_VERTTIMING_VND2_N(N)(((N)-1)<<18)
#define LCD_VERTTIMING_VND1_N(N)(((N)-1)<<9)
#define LCD_VERTTIMING_VPW_N(N) (((N)-1)<<0)
/* lcd_clkcontrol */
#define LCD_CLKCONTROL_EXT (1<<22)
#define LCD_CLKCONTROL_DELAY (3<<20)
#define LCD_CLKCONTROL_CDD (1<<19)
#define LCD_CLKCONTROL_IB (1<<18)
#define LCD_CLKCONTROL_IC (1<<17)
#define LCD_CLKCONTROL_IH (1<<16)
#define LCD_CLKCONTROL_IV (1<<15)
#define LCD_CLKCONTROL_BF (0x1F<<10)
#define LCD_CLKCONTROL_PCD (0x3FF<<0)
#define LCD_CLKCONTROL_BF_N(N) (((N)-1)<<10)
#define LCD_CLKCONTROL_PCD_N(N) ((N)<<0)
/* lcd_pwmdiv */
#define LCD_PWMDIV_EN (1<<31)
#define LCD_PWMDIV_PWMDIV (0x1FFFF<<0)
#define LCD_PWMDIV_PWMDIV_N(N) ((N)<<0)
/* lcd_pwmhi */
#define LCD_PWMHI_PWMHI1 (0xFFFF<<16)
#define LCD_PWMHI_PWMHI0 (0xFFFF<<0)
#define LCD_PWMHI_PWMHI1_N(N) ((N)<<16)
#define LCD_PWMHI_PWMHI0_N(N) ((N)<<0)
/* lcd_hwccon */
#define LCD_HWCCON_EN (1<<0)
/* lcd_cursorpos */
#define LCD_CURSORPOS_HWCXOFF (0x1F<<27)
#define LCD_CURSORPOS_HWCXPOS (0x07FF<<16)
#define LCD_CURSORPOS_HWCYOFF (0x1F<<11)
#define LCD_CURSORPOS_HWCYPOS (0x07FF<<0)
#define LCD_CURSORPOS_HWCXOFF_N(N) ((N)<<27)
#define LCD_CURSORPOS_HWCXPOS_N(N) ((N)<<16)
#define LCD_CURSORPOS_HWCYOFF_N(N) ((N)<<11)
#define LCD_CURSORPOS_HWCYPOS_N(N) ((N)<<0)
/* lcd_cursorcolor */
#define LCD_CURSORCOLOR_HWCA (0xFF<<24)
#define LCD_CURSORCOLOR_HWCR (0xFF<<16)
#define LCD_CURSORCOLOR_HWCG (0xFF<<8)
#define LCD_CURSORCOLOR_HWCB (0xFF<<0)
#define LCD_CURSORCOLOR_HWCA_N(N) ((N)<<24)
#define LCD_CURSORCOLOR_HWCR_N(N) ((N)<<16)
#define LCD_CURSORCOLOR_HWCG_N(N) ((N)<<8)
#define LCD_CURSORCOLOR_HWCB_N(N) ((N)<<0)
/* lcd_fifoctrl */
#define LCD_FIFOCTRL_F3IF (1<<29)
#define LCD_FIFOCTRL_F3REQ (0x1F<<24)
#define LCD_FIFOCTRL_F2IF (1<<29)
#define LCD_FIFOCTRL_F2REQ (0x1F<<16)
#define LCD_FIFOCTRL_F1IF (1<<29)
#define LCD_FIFOCTRL_F1REQ (0x1F<<8)
#define LCD_FIFOCTRL_F0IF (1<<29)
#define LCD_FIFOCTRL_F0REQ (0x1F<<0)
#define LCD_FIFOCTRL_F3REQ_N(N) ((N-1)<<24)
#define LCD_FIFOCTRL_F2REQ_N(N) ((N-1)<<16)
#define LCD_FIFOCTRL_F1REQ_N(N) ((N-1)<<8)
#define LCD_FIFOCTRL_F0REQ_N(N) ((N-1)<<0)
/* lcd_outmask */
#define LCD_OUTMASK_MASK (0x00FFFFFF)
/********************************************************************/
#endif /* _AU1200LCD_H */

14
drivers/video/chipsfb.c
View file

@ -178,8 +178,6 @@ struct chips_init_reg {
unsigned char data;
};
#define N_ELTS(x) (sizeof(x) / sizeof(x[0]))
static struct chips_init_reg chips_init_sr[] = {
{ 0x00, 0x03 },
{ 0x01, 0x01 },
@ -287,18 +285,18 @@ static void __init chips_hw_init(void)
{
int i;
for (i = 0; i < N_ELTS(chips_init_xr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
outb(0x29, 0x3c2); /* set misc output reg */
for (i = 0; i < N_ELTS(chips_init_sr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
for (i = 0; i < N_ELTS(chips_init_gr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
for (i = 0; i < N_ELTS(chips_init_ar); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
for (i = 0; i < N_ELTS(chips_init_cr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
for (i = 0; i < N_ELTS(chips_init_fr); ++i)
for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
}

24
drivers/video/console/Kconfig
View file

@ -26,6 +26,30 @@ config VGA_CONSOLE
# fi
# fi
config VGACON_SOFT_SCROLLBACK
bool "Enable Scrollback Buffer in System RAM"
depends on VGA_CONSOLE
default n
help
The scrollback buffer of the standard VGA console is located in
the VGA RAM. The size of this RAM is fixed and is quite small.
If you require a larger scrollback buffer, this can be placed in
System RAM which is dynamically allocated during intialization.
Placing the scrollback buffer in System RAM will slightly slow
down the console.
If you want this feature, say 'Y' here and enter the amount of
RAM to allocate for this buffer. If unsure, say 'N'.
config VGACON_SOFT_SCROLLBACK_SIZE
int "Scrollback Buffer Size (in KB)"
depends on VGACON_SOFT_SCROLLBACK
default "64"
help
Enter the amount of System RAM to allocate for the scrollback
buffer. Each 64KB will give you approximately 16 80x25
screenfuls of scrollback buffer
config VIDEO_SELECT
bool "Video mode selection support"
depends on X86 && VGA_CONSOLE

2
drivers/video/console/fonts.c
View file

@ -66,7 +66,7 @@ static const struct font_desc *fonts[] = {
#endif
};
#define num_fonts (sizeof(fonts)/sizeof(*fonts))
#define num_fonts ARRAY_SIZE(fonts)
#ifdef NO_FONTS
#error No fonts configured.

4
drivers/video/console/newport_con.c
View file

@ -149,7 +149,7 @@ static inline void newport_clear_lines(int ystart, int yend, int ci)
newport_clear_screen(0, ystart, 1280 + 63, yend, ci);
}
void newport_reset(void)
static void newport_reset(void)
{
unsigned short treg;
int i;
@ -193,7 +193,7 @@ void newport_reset(void)
* calculate the actual screen size by reading
* the video timing out of the VC2
*/
void newport_get_screensize(void)
static void newport_get_screensize(void)
{
int i, cols;
unsigned short ventry, treg;

271
drivers/video/console/vgacon.c
View file

@ -93,7 +93,6 @@ static u8 vgacon_build_attr(struct vc_data *c, u8 color, u8 intensity,
static void vgacon_invert_region(struct vc_data *c, u16 * p, int count);
static unsigned long vgacon_uni_pagedir[2];
/* Description of the hardware situation */
static unsigned long vga_vram_base; /* Base of video memory */
static unsigned long vga_vram_end; /* End of video memory */
@ -161,6 +160,201 @@ static inline void write_vga(unsigned char reg, unsigned int val)
spin_unlock_irqrestore(&vga_lock, flags);
}
static inline void vga_set_mem_top(struct vc_data *c)
{
write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2);
}
#ifdef CONFIG_VGACON_SOFT_SCROLLBACK
#include <linux/bootmem.h>
/* software scrollback */
static void *vgacon_scrollback;
static int vgacon_scrollback_tail;
static int vgacon_scrollback_size;
static int vgacon_scrollback_rows;
static int vgacon_scrollback_cnt;
static int vgacon_scrollback_cur;
static int vgacon_scrollback_save;
static int vgacon_scrollback_restore;
static void vgacon_scrollback_init(int pitch)
{
int rows = CONFIG_VGACON_SOFT_SCROLLBACK_SIZE * 1024/pitch;
if (vgacon_scrollback) {
vgacon_scrollback_cnt = 0;
vgacon_scrollback_tail = 0;
vgacon_scrollback_cur = 0;
vgacon_scrollback_rows = rows - 1;
vgacon_scrollback_size = rows * pitch;
}
}
static void __init vgacon_scrollback_startup(void)
{
vgacon_scrollback = alloc_bootmem(CONFIG_VGACON_SOFT_SCROLLBACK_SIZE
* 1024);
vgacon_scrollback_init(vga_video_num_columns * 2);
}
static void vgacon_scrollback_update(struct vc_data *c, int t, int count)
{
void *p;
if (!vgacon_scrollback_size || c->vc_num != fg_console)
return;
p = (void *) (c->vc_origin + t * c->vc_size_row);
while (count--) {
scr_memcpyw(vgacon_scrollback + vgacon_scrollback_tail,
p, c->vc_size_row);
vgacon_scrollback_cnt++;
p += c->vc_size_row;
vgacon_scrollback_tail += c->vc_size_row;
if (vgacon_scrollback_tail >= vgacon_scrollback_size)
vgacon_scrollback_tail = 0;
if (vgacon_scrollback_cnt > vgacon_scrollback_rows)
vgacon_scrollback_cnt = vgacon_scrollback_rows;
vgacon_scrollback_cur = vgacon_scrollback_cnt;
}
}
static void vgacon_restore_screen(struct vc_data *c)
{
vgacon_scrollback_save = 0;
if (!vga_is_gfx && !vgacon_scrollback_restore) {
scr_memcpyw((u16 *) c->vc_origin, (u16 *) c->vc_screenbuf,
c->vc_screenbuf_size > vga_vram_size ?
vga_vram_size : c->vc_screenbuf_size);
vgacon_scrollback_restore = 1;
vgacon_scrollback_cur = vgacon_scrollback_cnt;
}
}
static int vgacon_scrolldelta(struct vc_data *c, int lines)
{
int start, end, count, soff, diff;
void *d, *s;
if (!lines) {
c->vc_visible_origin = c->vc_origin;
vga_set_mem_top(c);
return 1;
}
if (!vgacon_scrollback)
return 1;
if (!vgacon_scrollback_save) {
vgacon_cursor(c, CM_ERASE);
vgacon_save_screen(c);
vgacon_scrollback_save = 1;
}
vgacon_scrollback_restore = 0;
start = vgacon_scrollback_cur + lines;
end = start + abs(lines);
if (start < 0)
start = 0;
if (start > vgacon_scrollback_cnt)
start = vgacon_scrollback_cnt;
if (end < 0)
end = 0;
if (end > vgacon_scrollback_cnt)
end = vgacon_scrollback_cnt;
vgacon_scrollback_cur = start;
count = end - start;
soff = vgacon_scrollback_tail - ((vgacon_scrollback_cnt - end) *
c->vc_size_row);
soff -= count * c->vc_size_row;
if (soff < 0)
soff += vgacon_scrollback_size;
count = vgacon_scrollback_cnt - start;
if (count > c->vc_rows)
count = c->vc_rows;
diff = c->vc_rows - count;
d = (void *) c->vc_origin;
s = (void *) c->vc_screenbuf;
while (count--) {
scr_memcpyw(d, vgacon_scrollback + soff, c->vc_size_row);
d += c->vc_size_row;
soff += c->vc_size_row;
if (soff >= vgacon_scrollback_size)
soff = 0;
}
if (diff == c->vc_rows) {
vgacon_cursor(c, CM_MOVE);
} else {
while (diff--) {
scr_memcpyw(d, s, c->vc_size_row);
d += c->vc_size_row;
s += c->vc_size_row;
}
}
return 1;
}
#else
#define vgacon_scrollback_startup(...) do { } while (0)
#define vgacon_scrollback_init(...) do { } while (0)
#define vgacon_scrollback_update(...) do { } while (0)
static void vgacon_restore_screen(struct vc_data *c)
{
if (c->vc_origin != c->vc_visible_origin)
vgacon_scrolldelta(c, 0);
}
static int vgacon_scrolldelta(struct vc_data *c, int lines)
{
if (!lines) /* Turn scrollback off */
c->vc_visible_origin = c->vc_origin;
else {
int margin = c->vc_size_row * 4;
int ul, we, p, st;
if (vga_rolled_over >
(c->vc_scr_end - vga_vram_base) + margin) {
ul = c->vc_scr_end - vga_vram_base;
we = vga_rolled_over + c->vc_size_row;
} else {
ul = 0;
we = vga_vram_size;
}
p = (c->vc_visible_origin - vga_vram_base - ul + we) % we +
lines * c->vc_size_row;
st = (c->vc_origin - vga_vram_base - ul + we) % we;
if (st < 2 * margin)
margin = 0;
if (p < margin)
p = 0;
if (p > st - margin)
p = st;
c->vc_visible_origin = vga_vram_base + (p + ul) % we;
}
vga_set_mem_top(c);
return 1;
}
#endif /* CONFIG_VGACON_SOFT_SCROLLBACK */
static const char __init *vgacon_startup(void)
{
const char *display_desc = NULL;
@ -330,7 +524,7 @@ static const char __init *vgacon_startup(void)
vgacon_xres = ORIG_VIDEO_COLS * VGA_FONTWIDTH;
vgacon_yres = vga_scan_lines;
vgacon_scrollback_startup();
return display_desc;
}
@ -357,11 +551,6 @@ static void vgacon_init(struct vc_data *c, int init)
con_set_default_unimap(c);
}
static inline void vga_set_mem_top(struct vc_data *c)
{
write_vga(12, (c->vc_visible_origin - vga_vram_base) / 2);
}
static void vgacon_deinit(struct vc_data *c)
{
/* When closing the last console, reset video origin */
@ -433,29 +622,37 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
cursor_size_lastto = to;
spin_lock_irqsave(&vga_lock, flags);
outb_p(0x0a, vga_video_port_reg); /* Cursor start */
curs = inb_p(vga_video_port_val);
outb_p(0x0b, vga_video_port_reg); /* Cursor end */
cure = inb_p(vga_video_port_val);
if (vga_video_type >= VIDEO_TYPE_VGAC) {
outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
curs = inb_p(vga_video_port_val);
outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
cure = inb_p(vga_video_port_val);
} else {
curs = 0;
cure = 0;
}
curs = (curs & 0xc0) | from;
cure = (cure & 0xe0) | to;
outb_p(0x0a, vga_video_port_reg); /* Cursor start */
outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
outb_p(curs, vga_video_port_val);
outb_p(0x0b, vga_video_port_reg); /* Cursor end */
outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
outb_p(cure, vga_video_port_val);
spin_unlock_irqrestore(&vga_lock, flags);
}
static void vgacon_cursor(struct vc_data *c, int mode)
{
if (c->vc_origin != c->vc_visible_origin)
vgacon_scrolldelta(c, 0);
vgacon_restore_screen(c);
switch (mode) {
case CM_ERASE:
write_vga(14, (c->vc_pos - vga_vram_base) / 2);
vgacon_set_cursor_size(c->vc_x, 31, 30);
if (vga_video_type >= VIDEO_TYPE_VGAC)
vgacon_set_cursor_size(c->vc_x, 31, 30);
else
vgacon_set_cursor_size(c->vc_x, 31, 31);
break;
case CM_MOVE:
@ -493,7 +690,10 @@ static void vgacon_cursor(struct vc_data *c, int mode)
10 ? 1 : 2));
break;
case CUR_NONE:
vgacon_set_cursor_size(c->vc_x, 31, 30);
if (vga_video_type >= VIDEO_TYPE_VGAC)
vgacon_set_cursor_size(c->vc_x, 31, 30);
else
vgacon_set_cursor_size(c->vc_x, 31, 31);
break;
default:
vgacon_set_cursor_size(c->vc_x, 1,
@ -595,6 +795,7 @@ static int vgacon_switch(struct vc_data *c)
vgacon_doresize(c, c->vc_cols, c->vc_rows);
}
vgacon_scrollback_init(c->vc_size_row);
return 0; /* Redrawing not needed */
}
@ -1062,37 +1263,6 @@ static int vgacon_resize(struct vc_data *c, unsigned int width,
return 0;
}
static int vgacon_scrolldelta(struct vc_data *c, int lines)
{
if (!lines) /* Turn scrollback off */
c->vc_visible_origin = c->vc_origin;
else {
int margin = c->vc_size_row * 4;
int ul, we, p, st;
if (vga_rolled_over >
(c->vc_scr_end - vga_vram_base) + margin) {
ul = c->vc_scr_end - vga_vram_base;
we = vga_rolled_over + c->vc_size_row;
} else {
ul = 0;
we = vga_vram_size;
}
p = (c->vc_visible_origin - vga_vram_base - ul + we) % we +
lines * c->vc_size_row;
st = (c->vc_origin - vga_vram_base - ul + we) % we;
if (st < 2 * margin)
margin = 0;
if (p < margin)
p = 0;
if (p > st - margin)
p = st;
c->vc_visible_origin = vga_vram_base + (p + ul) % we;
}
vga_set_mem_top(c);
return 1;
}
static int vgacon_set_origin(struct vc_data *c)
{
if (vga_is_gfx || /* We don't play origin tricks in graphic modes */
@ -1135,15 +1305,14 @@ static int vgacon_scroll(struct vc_data *c, int t, int b, int dir,
if (t || b != c->vc_rows || vga_is_gfx)
return 0;
if (c->vc_origin != c->vc_visible_origin)
vgacon_scrolldelta(c, 0);
if (!vga_hardscroll_enabled || lines >= c->vc_rows / 2)
return 0;
vgacon_restore_screen(c);
oldo = c->vc_origin;
delta = lines * c->vc_size_row;
if (dir == SM_UP) {
vgacon_scrollback_update(c, t, lines);
if (c->vc_scr_end + delta >= vga_vram_end) {
scr_memcpyw((u16 *) vga_vram_base,
(u16 *) (oldo + delta),

4
drivers/video/fbcmap.c
View file

@ -85,7 +85,7 @@ static struct fb_cmap default_16_colors = {
* Allocates memory for a colormap @cmap. @len is the
* number of entries in the palette.
*
* Returns -1 errno on error, or zero on success.
* Returns negative errno on error, or zero on success.
*
*/
@ -116,7 +116,7 @@ int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp)
fail:
fb_dealloc_cmap(cmap);
return -1;
return -ENOMEM;
}
/**

31
drivers/video/fbmem.c
View file

@ -55,7 +55,7 @@
#define FBPIXMAPSIZE (1024 * 8)
static struct notifier_block *fb_notifier_list;
static BLOCKING_NOTIFIER_HEAD(fb_notifier_list);
struct fb_info *registered_fb[FB_MAX];
int num_registered_fb;
@ -784,7 +784,7 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
event.info = info;
event.data = &mode1;
ret = notifier_call_chain(&fb_notifier_list,
ret = blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_MODE_DELETE, &event);
}
@ -830,8 +830,8 @@ fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var)
info->flags &= ~FBINFO_MISC_USEREVENT;
event.info = info;
notifier_call_chain(&fb_notifier_list, evnt,
&event);
blocking_notifier_call_chain(&fb_notifier_list,
evnt, &event);
}
}
}
@ -854,7 +854,8 @@ fb_blank(struct fb_info *info, int blank)
event.info = info;
event.data = &blank;
notifier_call_chain(&fb_notifier_list, FB_EVENT_BLANK, &event);
blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_BLANK, &event);
}
return ret;
@ -925,7 +926,7 @@ fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
con2fb.framebuffer = -1;
event.info = info;
event.data = &con2fb;
notifier_call_chain(&fb_notifier_list,
blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_GET_CONSOLE_MAP, &event);
return copy_to_user(argp, &con2fb,
sizeof(con2fb)) ? -EFAULT : 0;
@ -944,7 +945,7 @@ fb_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
return -EINVAL;
event.info = info;
event.data = &con2fb;
return notifier_call_chain(&fb_notifier_list,
return blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_SET_CONSOLE_MAP,
&event);
case FBIOBLANK:
@ -1324,7 +1325,7 @@ register_framebuffer(struct fb_info *fb_info)
devfs_mk_cdev(MKDEV(FB_MAJOR, i),
S_IFCHR | S_IRUGO | S_IWUGO, "fb/%d", i);
event.info = fb_info;
notifier_call_chain(&fb_notifier_list,
blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_FB_REGISTERED, &event);
return 0;
}
@ -1366,7 +1367,7 @@ unregister_framebuffer(struct fb_info *fb_info)
*/
int fb_register_client(struct notifier_block *nb)
{
return notifier_chain_register(&fb_notifier_list, nb);
return blocking_notifier_chain_register(&fb_notifier_list, nb);
}
/**
@ -1375,7 +1376,7 @@ int fb_register_client(struct notifier_block *nb)
*/
int fb_unregister_client(struct notifier_block *nb)
{
return notifier_chain_unregister(&fb_notifier_list, nb);
return blocking_notifier_chain_unregister(&fb_notifier_list, nb);
}
/**
@ -1393,11 +1394,13 @@ void fb_set_suspend(struct fb_info *info, int state)
event.info = info;
if (state) {
notifier_call_chain(&fb_notifier_list, FB_EVENT_SUSPEND, &event);
blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_SUSPEND, &event);
info->state = FBINFO_STATE_SUSPENDED;
} else {
info->state = FBINFO_STATE_RUNNING;
notifier_call_chain(&fb_notifier_list, FB_EVENT_RESUME, &event);
blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_RESUME, &event);
}
}
@ -1469,7 +1472,7 @@ int fb_new_modelist(struct fb_info *info)
if (!list_empty(&info->modelist)) {
event.info = info;
err = notifier_call_chain(&fb_notifier_list,
err = blocking_notifier_call_chain(&fb_notifier_list,
FB_EVENT_NEW_MODELIST,
&event);
}
@ -1495,7 +1498,7 @@ int fb_con_duit(struct fb_info *info, int event, void *data)
evnt.info = info;
evnt.data = data;
return notifier_call_chain(&fb_notifier_list, event, &evnt);
return blocking_notifier_call_chain(&fb_notifier_list, event, &evnt);
}
EXPORT_SYMBOL(fb_con_duit);

6
drivers/video/fbmon.c
View file

@ -1281,7 +1281,7 @@ int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info)
-EINVAL : 0;
}
#if defined(__i386__)
#if defined(CONFIG_FB_FIRMWARE_EDID) && defined(__i386__)
#include <linux/pci.h>
/*
@ -1311,11 +1311,11 @@ const unsigned char *fb_firmware_edid(struct device *device)
{
return NULL;
}
#endif /* _i386_ */
#endif
EXPORT_SYMBOL(fb_firmware_edid);
EXPORT_SYMBOL(fb_parse_edid);
EXPORT_SYMBOL(fb_edid_to_monspecs);
EXPORT_SYMBOL(fb_firmware_edid);
EXPORT_SYMBOL(fb_get_mode);
EXPORT_SYMBOL(fb_validate_mode);
EXPORT_SYMBOL(fb_destroy_modedb);

4
drivers/video/fbsysfs.c
View file

@ -348,7 +348,7 @@ static ssize_t store_cmap(struct class_device *class_device, const char *buf,
fb_copy_cmap(&umap, &fb_info->cmap);
fb_dealloc_cmap(&umap);
return rc;
return rc ?: count;
}
for (i = 0; i < length; i++) {
u16 red, blue, green, tsp;
@ -367,7 +367,7 @@ static ssize_t store_cmap(struct class_device *class_device, const char *buf,
if (transp)
fb_info->cmap.transp[i] = tsp;
}
return 0;
return count;
}
static ssize_t show_cmap(struct class_device *class_device, char *buf)

17
drivers/video/geode/Kconfig
View file

@ -8,9 +8,24 @@ config FB_GEODE
Say 'Y' here to allow you to select framebuffer drivers for
the AMD Geode family of processors.
config FB_GEODE_GX
tristate "AMD Geode GX framebuffer support (EXPERIMENTAL)"
depends on FB && FB_GEODE && EXPERIMENTAL
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Framebuffer driver for the display controller integrated into the
AMD Geode GX processors.
To compile this driver as a module, choose M here: the module will be
called gxfb.
If unsure, say N.
config FB_GEODE_GX1
tristate "AMD Geode GX1 framebuffer support (EXPERIMENTAL)"
depends on FB_GEODE && EXPERIMENTAL
depends on FB && FB_GEODE && EXPERIMENTAL
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT

4
drivers/video/geode/Makefile
View file

@ -1,5 +1,7 @@
# Makefile for the Geode family framebuffer drivers
obj-$(CONFIG_FB_GEODE_GX1) += gx1fb.o
obj-$(CONFIG_FB_GEODE_GX) += gxfb.o
gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
gx1fb-objs := gx1fb_core.o display_gx1.o video_cs5530.o
gxfb-objs := gxfb_core.o display_gx.o video_gx.o

156
drivers/video/geode/display_gx.c Normal file
View file

@ -0,0 +1,156 @@
/*
* Geode GX display controller.
*
* Copyright (C) 2005 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by * the
* Free Software Foundation; either version 2 of the License, or * (at your
* option) any later version.
*/
#include <linux/spinlock.h>
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/div64.h>
#include <asm/delay.h>
#include "geodefb.h"
#include "display_gx.h"
int gx_frame_buffer_size(void)
{
/* Assuming 16 MiB. */
return 16*1024*1024;
}
int gx_line_delta(int xres, int bpp)
{
/* Must be a multiple of 8 bytes. */
return (xres * (bpp >> 3) + 7) & ~0x7;
}
static void gx_set_mode(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 gcfg, dcfg;
int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
/* Unlock the display controller registers. */
readl(par->dc_regs + DC_UNLOCK);
writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
/* Disable the timing generator. */
dcfg &= ~(DC_DCFG_TGEN);
writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
/* Wait for pending memory requests before disabling the FIFO load. */
udelay(100);
/* Disable FIFO load and compression. */
gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
/* Setup DCLK and its divisor. */
par->vid_ops->set_dclk(info);
/*
* Setup new mode.
*/
/* Clear all unused feature bits. */
gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
dcfg = 0;
/* Set FIFO priority (default 6/5) and enable. */
/* FIXME: increase fifo priority for 1280x1024 and higher modes? */
gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
/* Framebuffer start offset. */
writel(0, par->dc_regs + DC_FB_ST_OFFSET);
/* Line delta and line buffer length. */
writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
par->dc_regs + DC_LINE_SIZE);
/* Enable graphics and video data and unmask address lines. */
dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
/* Set pixel format. */
switch (info->var.bits_per_pixel) {
case 8:
dcfg |= DC_DCFG_DISP_MODE_8BPP;
break;
case 16:
dcfg |= DC_DCFG_DISP_MODE_16BPP;
dcfg |= DC_DCFG_16BPP_MODE_565;
break;
case 32:
dcfg |= DC_DCFG_DISP_MODE_24BPP;
dcfg |= DC_DCFG_PALB;
break;
}
/* Enable timing generator. */
dcfg |= DC_DCFG_TGEN;
/* Horizontal and vertical timings. */
hactive = info->var.xres;
hblankstart = hactive;
hsyncstart = hblankstart + info->var.right_margin;
hsyncend = hsyncstart + info->var.hsync_len;
hblankend = hsyncend + info->var.left_margin;
htotal = hblankend;
vactive = info->var.yres;
vblankstart = vactive;
vsyncstart = vblankstart + info->var.lower_margin;
vsyncend = vsyncstart + info->var.vsync_len;
vblankend = vsyncend + info->var.upper_margin;
vtotal = vblankend;
writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
/* Write final register values. */
writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
par->vid_ops->configure_display(info);
/* Relock display controller registers */
writel(0, par->dc_regs + DC_UNLOCK);
}
static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
unsigned red, unsigned green, unsigned blue)
{
struct geodefb_par *par = info->par;
int val;
/* Hardware palette is in RGB 8-8-8 format. */
val = (red << 8) & 0xff0000;
val |= (green) & 0x00ff00;
val |= (blue >> 8) & 0x0000ff;
writel(regno, par->dc_regs + DC_PAL_ADDRESS);
writel(val, par->dc_regs + DC_PAL_DATA);
}
struct geode_dc_ops gx_dc_ops = {
.set_mode = gx_set_mode,
.set_palette_reg = gx_set_hw_palette_reg,
};

96
drivers/video/geode/display_gx.h Normal file
View file

@ -0,0 +1,96 @@
/*
* Geode GX display controller
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DISPLAY_GX_H__
#define __DISPLAY_GX_H__
int gx_frame_buffer_size(void);
int gx_line_delta(int xres, int bpp);
extern struct geode_dc_ops gx_dc_ops;
/* Display controller registers */
#define DC_UNLOCK 0x00
# define DC_UNLOCK_CODE 0x00004758
#define DC_GENERAL_CFG 0x04
# define DC_GCFG_DFLE 0x00000001
# define DC_GCFG_CURE 0x00000002
# define DC_GCFG_ICNE 0x00000004
# define DC_GCFG_VIDE 0x00000008
# define DC_GCFG_CMPE 0x00000020
# define DC_GCFG_DECE 0x00000040
# define DC_GCFG_VGAE 0x00000080
# define DC_GCFG_DFHPSL_MASK 0x00000F00
# define DC_GCFG_DFHPSL_POS 8
# define DC_GCFG_DFHPEL_MASK 0x0000F000
# define DC_GCFG_DFHPEL_POS 12
# define DC_GCFG_STFM 0x00010000
# define DC_GCFG_FDTY 0x00020000
# define DC_GCFG_VGAFT 0x00040000
# define DC_GCFG_VDSE 0x00080000
# define DC_GCFG_YUVM 0x00100000
# define DC_GCFG_VFSL 0x00800000
# define DC_GCFG_SIGE 0x01000000
# define DC_GCFG_SGRE 0x02000000
# define DC_GCFG_SGFR 0x04000000
# define DC_GCFG_CRC_MODE 0x08000000
# define DC_GCFG_DIAG 0x10000000
# define DC_GCFG_CFRW 0x20000000
#define DC_DISPLAY_CFG 0x08
# define DC_DCFG_TGEN 0x00000001
# define DC_DCFG_GDEN 0x00000008
# define DC_DCFG_VDEN 0x00000010
# define DC_DCFG_TRUP 0x00000040
# define DC_DCFG_DISP_MODE_MASK 0x00000300
# define DC_DCFG_DISP_MODE_8BPP 0x00000000
# define DC_DCFG_DISP_MODE_16BPP 0x00000100
# define DC_DCFG_DISP_MODE_24BPP 0x00000200
# define DC_DCFG_16BPP_MODE_MASK 0x00000c00
# define DC_DCFG_16BPP_MODE_565 0x00000000
# define DC_DCFG_16BPP_MODE_555 0x00000100
# define DC_DCFG_16BPP_MODE_444 0x00000200
# define DC_DCFG_DCEN 0x00080000
# define DC_DCFG_PALB 0x02000000
# define DC_DCFG_FRLK 0x04000000
# define DC_DCFG_VISL 0x08000000
# define DC_DCFG_FRSL 0x20000000
# define DC_DCFG_A18M 0x40000000
# define DC_DCFG_A20M 0x80000000
#define DC_FB_ST_OFFSET 0x10
#define DC_LINE_SIZE 0x30
# define DC_LINE_SIZE_FB_LINE_SIZE_MASK 0x000007ff
# define DC_LINE_SIZE_FB_LINE_SIZE_POS 0
# define DC_LINE_SIZE_CB_LINE_SIZE_MASK 0x007f0000
# define DC_LINE_SIZE_CB_LINE_SIZE_POS 16
# define DC_LINE_SIZE_VID_LINE_SIZE_MASK 0xff000000
# define DC_LINE_SIZE_VID_LINE_SIZE_POS 24
#define DC_GFX_PITCH 0x34
# define DC_GFX_PITCH_FB_PITCH_MASK 0x0000ffff
# define DC_GFX_PITCH_FB_PITCH_POS 0
# define DC_GFX_PITCH_CB_PITCH_MASK 0xffff0000
# define DC_GFX_PITCH_CB_PITCH_POS 16
#define DC_H_ACTIVE_TIMING 0x40
#define DC_H_BLANK_TIMING 0x44
#define DC_H_SYNC_TIMING 0x48
#define DC_V_ACTIVE_TIMING 0x50
#define DC_V_BLANK_TIMING 0x54
#define DC_V_SYNC_TIMING 0x58
#define DC_PAL_ADDRESS 0x70
#define DC_PAL_DATA 0x74
#endif /* !__DISPLAY_GX1_H__ */

423
drivers/video/geode/gxfb_core.c Normal file
View file

@ -0,0 +1,423 @@
/*
* Geode GX framebuffer driver.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
* This driver assumes that the BIOS has created a virtual PCI device header
* for the video device. The PCI header is assumed to contain the following
* BARs:
*
* BAR0 - framebuffer memory
* BAR1 - graphics processor registers
* BAR2 - display controller registers
* BAR3 - video processor and flat panel control registers.
*
* 16 MiB of framebuffer memory is assumed to be available.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/tty.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include "geodefb.h"
#include "display_gx.h"
#include "video_gx.h"
static char mode_option[32] = "640x480-16@60";
/* Modes relevant to the GX (taken from modedb.c) */
static const struct fb_videomode __initdata gx_modedb[] = {
/* 640x480-60 VESA */
{ NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-75 VESA */
{ NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 640x480-85 VESA */
{ NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-60 VESA */
{ NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-75 VESA */
{ NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 800x600-85 VESA */
{ NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-60 VESA */
{ NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
0, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-75 VESA */
{ NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1024x768-85 VESA */
{ NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-60 VESA */
{ NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x960-85 VESA */
{ NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-60 VESA */
{ NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-75 VESA */
{ NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1280x1024-85 VESA */
{ NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-60 VESA */
{ NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-75 VESA */
{ NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
/* 1600x1200-85 VESA */
{ NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
};
static int gxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
if (var->xres > 1600 || var->yres > 1200)
return -EINVAL;
if ((var->xres > 1280 || var->yres > 1024) && var->bits_per_pixel > 16)
return -EINVAL;
if (var->bits_per_pixel == 32) {
var->red.offset = 16; var->red.length = 8;
var->green.offset = 8; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else if (var->bits_per_pixel == 16) {
var->red.offset = 11; var->red.length = 5;
var->green.offset = 5; var->green.length = 6;
var->blue.offset = 0; var->blue.length = 5;
} else if (var->bits_per_pixel == 8) {
var->red.offset = 0; var->red.length = 8;
var->green.offset = 0; var->green.length = 8;
var->blue.offset = 0; var->blue.length = 8;
} else
return -EINVAL;
var->transp.offset = 0; var->transp.length = 0;
/* Enough video memory? */
if (gx_line_delta(var->xres, var->bits_per_pixel) * var->yres > info->fix.smem_len)
return -EINVAL;
/* FIXME: Check timing parameters here? */
return 0;
}
static int gxfb_set_par(struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.bits_per_pixel > 8) {
info->fix.visual = FB_VISUAL_TRUECOLOR;
fb_dealloc_cmap(&info->cmap);
} else {
info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
fb_alloc_cmap(&info->cmap, 1<<info->var.bits_per_pixel, 0);
}
info->fix.line_length = gx_line_delta(info->var.xres, info->var.bits_per_pixel);
par->dc_ops->set_mode(info);
return 0;
}
static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
{
chan &= 0xffff;
chan >>= 16 - bf->length;
return chan << bf->offset;
}
static int gxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
unsigned blue, unsigned transp,
struct fb_info *info)
{
struct geodefb_par *par = info->par;
if (info->var.grayscale) {
/* grayscale = 0.30*R + 0.59*G + 0.11*B */
red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
}
/* Truecolor has hardware independent palette */
if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
u32 *pal = info->pseudo_palette;
u32 v;
if (regno >= 16)
return -EINVAL;
v = chan_to_field(red, &info->var.red);
v |= chan_to_field(green, &info->var.green);
v |= chan_to_field(blue, &info->var.blue);
pal[regno] = v;
} else {
if (regno >= 256)
return -EINVAL;
par->dc_ops->set_palette_reg(info, regno, red, green, blue);
}
return 0;
}
static int gxfb_blank(int blank_mode, struct fb_info *info)
{
struct geodefb_par *par = info->par;
return par->vid_ops->blank_display(info, blank_mode);
}
static int __init gxfb_map_video_memory(struct fb_info *info, struct pci_dev *dev)
{
struct geodefb_par *par = info->par;
int fb_len;
int ret;
ret = pci_enable_device(dev);
if (ret < 0)
return ret;
ret = pci_request_region(dev, 3, "gxfb (video processor)");
if (ret < 0)
return ret;
par->vid_regs = ioremap(pci_resource_start(dev, 3),
pci_resource_len(dev, 3));
if (!par->vid_regs)
return -ENOMEM;
ret = pci_request_region(dev, 2, "gxfb (display controller)");
if (ret < 0)
return ret;
par->dc_regs = ioremap(pci_resource_start(dev, 2), pci_resource_len(dev, 2));
if (!par->dc_regs)
return -ENOMEM;
ret = pci_request_region(dev, 0, "gxfb (framebuffer)");
if (ret < 0)
return ret;
if ((fb_len = gx_frame_buffer_size()) < 0)
return -ENOMEM;
info->fix.smem_start = pci_resource_start(dev, 0);
info->fix.smem_len = fb_len;
info->screen_base = ioremap(info->fix.smem_start, info->fix.smem_len);
if (!info->screen_base)
return -ENOMEM;
dev_info(&dev->dev, "%d Kibyte of video memory at 0x%lx\n",
info->fix.smem_len / 1024, info->fix.smem_start);
return 0;
}
static struct fb_ops gxfb_ops = {
.owner = THIS_MODULE,
.fb_check_var = gxfb_check_var,
.fb_set_par = gxfb_set_par,
.fb_setcolreg = gxfb_setcolreg,
.fb_blank = gxfb_blank,
/* No HW acceleration for now. */
.fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit,
};
static struct fb_info * __init gxfb_init_fbinfo(struct device *dev)
{
struct geodefb_par *par;
struct fb_info *info;
/* Alloc enough space for the pseudo palette. */
info = framebuffer_alloc(sizeof(struct geodefb_par) + sizeof(u32) * 16, dev);
if (!info)
return NULL;
par = info->par;
strcpy(info->fix.id, "Geode GX");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.xpanstep = 0;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->var.nonstd = 0;
info->var.activate = FB_ACTIVATE_NOW;
info->var.height = -1;
info->var.width = -1;
info->var.accel_flags = 0;
info->var.vmode = FB_VMODE_NONINTERLACED;
info->fbops = &gxfb_ops;
info->flags = FBINFO_DEFAULT;
info->node = -1;
info->pseudo_palette = (void *)par + sizeof(struct geodefb_par);
info->var.grayscale = 0;
return info;
}
static int __init gxfb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct geodefb_par *par;
struct fb_info *info;
int ret;
info = gxfb_init_fbinfo(&pdev->dev);
if (!info)
return -ENOMEM;
par = info->par;
/* GX display controller and GX video device. */
par->dc_ops = &gx_dc_ops;
par->vid_ops = &gx_vid_ops;
if ((ret = gxfb_map_video_memory(info, pdev)) < 0) {
dev_err(&pdev->dev, "failed to map frame buffer or controller registers\n");
goto err;
}
ret = fb_find_mode(&info->var, info, mode_option,
gx_modedb, ARRAY_SIZE(gx_modedb), NULL, 16);
if (ret == 0 || ret == 4) {
dev_err(&pdev->dev, "could not find valid video mode\n");
ret = -EINVAL;
goto err;
}
/* Clear the frame buffer of garbage. */
memset_io(info->screen_base, 0, info->fix.smem_len);
gxfb_check_var(&info->var, info);
gxfb_set_par(info);
if (register_framebuffer(info) < 0) {
ret = -EINVAL;
goto err;
}
pci_set_drvdata(pdev, info);
printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id);
return 0;
err:
if (info->screen_base) {
iounmap(info->screen_base);
pci_release_region(pdev, 0);
}
if (par->vid_regs) {
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
}
if (par->dc_regs) {
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
}
pci_disable_device(pdev);
if (info)
framebuffer_release(info);
return ret;
}
static void gxfb_remove(struct pci_dev *pdev)
{
struct fb_info *info = pci_get_drvdata(pdev);
struct geodefb_par *par = info->par;
unregister_framebuffer(info);
iounmap((void __iomem *)info->screen_base);
pci_release_region(pdev, 0);
iounmap(par->vid_regs);
pci_release_region(pdev, 3);
iounmap(par->dc_regs);
pci_release_region(pdev, 2);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
framebuffer_release(info);
}
static struct pci_device_id gxfb_id_table[] = {
{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_VIDEO,
PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
0xff0000, 0 },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, gxfb_id_table);
static struct pci_driver gxfb_driver = {
.name = "gxfb",
.id_table = gxfb_id_table,
.probe = gxfb_probe,
.remove = gxfb_remove,
};
static int __init gxfb_init(void)
{
#ifndef MODULE
if (fb_get_options("gxfb", NULL))
return -ENODEV;
#endif
return pci_register_driver(&gxfb_driver);
}
static void __exit gxfb_cleanup(void)
{
pci_unregister_driver(&gxfb_driver);
}
module_init(gxfb_init);
module_exit(gxfb_cleanup);
module_param_string(mode, mode_option, sizeof(mode_option), 0444);
MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
MODULE_DESCRIPTION("Framebuffer driver for the AMD Geode GX");
MODULE_LICENSE("GPL");

262
drivers/video/geode/video_gx.c Normal file
View file

@ -0,0 +1,262 @@
/*
* Geode GX video processor device.
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* Portions from AMD's original 2.4 driver:
* Copyright (C) 2004 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/fb.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/msr.h>
#include "geodefb.h"
#include "video_gx.h"
/*
* Tables of register settings for various DOTCLKs.
*/
struct gx_pll_entry {
long pixclock; /* ps */
u32 sys_rstpll_bits;
u32 dotpll_value;
};
#define POSTDIV3 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
#define PREMULT2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPREMULT2)
#define PREDIV2 ((u32)MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3)
static const struct gx_pll_entry gx_pll_table_48MHz[] = {
{ 40123, POSTDIV3, 0x00000BF2 }, /* 24.9230 */
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, POSTDIV3|PREMULT2, 0x00000B1A }, /* 28.3220 */
{ 31746, POSTDIV3, 0x000002D2 }, /* 31.5000 */
{ 27777, POSTDIV3|PREMULT2, 0x00000FE2 }, /* 36.0000 */
{ 26666, POSTDIV3, 0x0000057A }, /* 37.5000 */
{ 25000, POSTDIV3, 0x0000030A }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, PREMULT2, 0x00000037 }, /* 50.3500 */
{ 18518, POSTDIV3|PREMULT2, 0x00000B0D }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000007F7 }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, PREMULT2, 0x00000707 }, /* 59.0000 */
{ 15873, POSTDIV3|PREMULT2, 0x00000B39 }, /* 63.0000 */
{ 15384, POSTDIV3|PREMULT2, 0x00000B45 }, /* 65.0000 */
{ 14814, POSTDIV3|PREMULT2, 0x00000FC1 }, /* 67.5000 */
{ 14124, POSTDIV3, 0x00000561 }, /* 70.8000 */
{ 13888, POSTDIV3, 0x000007E1 }, /* 72.0000 */
{ 13426, PREMULT2, 0x00000F4A }, /* 74.4810 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, POSTDIV3|PREMULT2, 0x00000709 }, /* 80.0000 */
{ 11135, PREMULT2, 0x00000262 }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, PREMULT2, 0x00000B4A }, /* 99.0000 */
{ 10000, PREMULT2, 0x00000036 }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000007F6 }, /* 112.5000 */
{ 7692, POSTDIV3|PREMULT2, 0x00000FB0 }, /* 130.0000 */
{ 7407, POSTDIV3|PREMULT2, 0x00000B50 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5787, PREMULT2, 0x0000002D }, /* 172.798 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x000002D1 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
static const struct gx_pll_entry gx_pll_table_14MHz[] = {
{ 39721, 0, 0x00000037 }, /* 25.1750 */
{ 35308, 0, 0x00000B7B }, /* 28.3220 */
{ 31746, 0, 0x000004D3 }, /* 31.5000 */
{ 27777, 0, 0x00000BE3 }, /* 36.0000 */
{ 26666, 0, 0x0000074F }, /* 37.5000 */
{ 25000, 0, 0x0000050B }, /* 40.0000 */
{ 22271, 0, 0x00000063 }, /* 44.9000 */
{ 20202, 0, 0x0000054B }, /* 49.5000 */
{ 20000, 0, 0x0000026E }, /* 50.0000 */
{ 19860, 0, 0x000007C3 }, /* 50.3500 */
{ 18518, 0, 0x000007E3 }, /* 54.0000 */
{ 17777, 0, 0x00000577 }, /* 56.2500 */
{ 17733, 0, 0x000002FB }, /* 56.3916 */
{ 17653, 0, 0x0000057B }, /* 56.6444 */
{ 16949, 0, 0x0000058B }, /* 59.0000 */
{ 15873, 0, 0x0000095E }, /* 63.0000 */
{ 15384, 0, 0x0000096A }, /* 65.0000 */
{ 14814, 0, 0x00000BC2 }, /* 67.5000 */
{ 14124, 0, 0x0000098A }, /* 70.8000 */
{ 13888, 0, 0x00000BE2 }, /* 72.0000 */
{ 13333, 0, 0x00000052 }, /* 75.0000 */
{ 12698, 0, 0x00000056 }, /* 78.7500 */
{ 12500, 0, 0x0000050A }, /* 80.0000 */
{ 11135, 0, 0x0000078E }, /* 89.8000 */
{ 10582, 0, 0x000002D2 }, /* 94.5000 */
{ 10101, 0, 0x000011F6 }, /* 99.0000 */
{ 10000, 0, 0x0000054E }, /* 100.0000 */
{ 9259, 0, 0x000007E2 }, /* 108.0000 */
{ 8888, 0, 0x000002FA }, /* 112.5000 */
{ 7692, 0, 0x00000BB1 }, /* 130.0000 */
{ 7407, 0, 0x00000975 }, /* 135.0000 */
{ 6349, 0, 0x00000055 }, /* 157.5000 */
{ 6172, 0, 0x000009C1 }, /* 162.0000 */
{ 5698, 0, 0x000002C1 }, /* 175.5000 */
{ 5291, 0, 0x00000539 }, /* 189.0000 */
{ 4938, 0, 0x00000551 }, /* 202.5000 */
{ 4357, 0, 0x0000057D }, /* 229.5000 */
};
static void gx_set_dclk_frequency(struct fb_info *info)
{
const struct gx_pll_entry *pll_table;
int pll_table_len;
int i, best_i;
long min, diff;
u64 dotpll, sys_rstpll;
int timeout = 1000;
/* Rev. 1 Geode GXs use a 14 MHz reference clock instead of 48 MHz. */
if (cpu_data->x86_mask == 1) {
pll_table = gx_pll_table_14MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_14MHz);
} else {
pll_table = gx_pll_table_48MHz;
pll_table_len = ARRAY_SIZE(gx_pll_table_48MHz);
}
/* Search the table for the closest pixclock. */
best_i = 0;
min = abs(pll_table[0].pixclock - info->var.pixclock);
for (i = 1; i < pll_table_len; i++) {
diff = abs(pll_table[i].pixclock - info->var.pixclock);
if (diff < min) {
min = diff;
best_i = i;
}
}
rdmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program new M, N and P. */
dotpll &= 0x00000000ffffffffull;
dotpll |= (u64)pll_table[best_i].dotpll_value << 32;
dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Program dividers. */
sys_rstpll &= ~( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2
| MSR_GLCP_SYS_RSTPLL_DOTPREMULT2
| MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 );
sys_rstpll |= pll_table[best_i].sys_rstpll_bits;
wrmsrl(MSR_GLCP_SYS_RSTPLL, sys_rstpll);
/* Clear reset bit to start PLL. */
dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
wrmsrl(MSR_GLCP_DOTPLL, dotpll);
/* Wait for LOCK bit. */
do {
rdmsrl(MSR_GLCP_DOTPLL, dotpll);
} while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
}
static void gx_configure_display(struct fb_info *info)
{
struct geodefb_par *par = info->par;
u32 dcfg, fp_pm;
dcfg = readl(par->vid_regs + GX_DCFG);
/* Clear bits from existing mode. */
dcfg &= ~(GX_DCFG_CRT_SYNC_SKW_MASK
| GX_DCFG_CRT_HSYNC_POL | GX_DCFG_CRT_VSYNC_POL
| GX_DCFG_VSYNC_EN | GX_DCFG_HSYNC_EN);
/* Set default sync skew. */
dcfg |= GX_DCFG_CRT_SYNC_SKW_DFLT;
/* Enable hsync and vsync. */
dcfg |= GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN;
/* Sync polarities. */
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
dcfg |= GX_DCFG_CRT_HSYNC_POL;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
dcfg |= GX_DCFG_CRT_VSYNC_POL;
writel(dcfg, par->vid_regs + GX_DCFG);
/* Power on flat panel. */
fp_pm = readl(par->vid_regs + GX_FP_PM);
fp_pm |= GX_FP_PM_P;
writel(fp_pm, par->vid_regs + GX_FP_PM);
}
static int gx_blank_display(struct fb_info *info, int blank_mode)
{
struct geodefb_par *par = info->par;
u32 dcfg, fp_pm;
int blank, hsync, vsync;
/* CRT power saving modes. */
switch (blank_mode) {
case FB_BLANK_UNBLANK:
blank = 0; hsync = 1; vsync = 1;
break;
case FB_BLANK_NORMAL:
blank = 1; hsync = 1; vsync = 1;
break;
case FB_BLANK_VSYNC_SUSPEND:
blank = 1; hsync = 1; vsync = 0;
break;
case FB_BLANK_HSYNC_SUSPEND:
blank = 1; hsync = 0; vsync = 1;
break;
case FB_BLANK_POWERDOWN:
blank = 1; hsync = 0; vsync = 0;
break;
default:
return -EINVAL;
}
dcfg = readl(par->vid_regs + GX_DCFG);
dcfg &= ~(GX_DCFG_DAC_BL_EN
| GX_DCFG_HSYNC_EN | GX_DCFG_VSYNC_EN);
if (!blank)
dcfg |= GX_DCFG_DAC_BL_EN;
if (hsync)
dcfg |= GX_DCFG_HSYNC_EN;
if (vsync)
dcfg |= GX_DCFG_VSYNC_EN;
writel(dcfg, par->vid_regs + GX_DCFG);
/* Power on/off flat panel. */
fp_pm = readl(par->vid_regs + GX_FP_PM);
if (blank_mode == FB_BLANK_POWERDOWN)
fp_pm &= ~GX_FP_PM_P;
else
fp_pm |= GX_FP_PM_P;
writel(fp_pm, par->vid_regs + GX_FP_PM);
return 0;
}
struct geode_vid_ops gx_vid_ops = {
.set_dclk = gx_set_dclk_frequency,
.configure_display = gx_configure_display,
.blank_display = gx_blank_display,
};

47
drivers/video/geode/video_gx.h Normal file
View file

@ -0,0 +1,47 @@
/*
* Geode GX video device
*
* Copyright (C) 2006 Arcom Control Systems Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __VIDEO_GX_H__
#define __VIDEO_GX_H__
extern struct geode_vid_ops gx_vid_ops;
/* Geode GX video processor registers */
#define GX_DCFG 0x0008
# define GX_DCFG_CRT_EN 0x00000001
# define GX_DCFG_HSYNC_EN 0x00000002
# define GX_DCFG_VSYNC_EN 0x00000004
# define GX_DCFG_DAC_BL_EN 0x00000008
# define GX_DCFG_CRT_HSYNC_POL 0x00000100
# define GX_DCFG_CRT_VSYNC_POL 0x00000200
# define GX_DCFG_CRT_SYNC_SKW_MASK 0x0001C000
# define GX_DCFG_CRT_SYNC_SKW_DFLT 0x00010000
# define GX_DCFG_VG_CK 0x00100000
# define GX_DCFG_GV_GAM 0x00200000
# define GX_DCFG_DAC_VREF 0x04000000
/* Geode GX flat panel display control registers */
#define GX_FP_PM 0x410
# define GX_FP_PM_P 0x01000000
/* Geode GX clock control MSRs */
#define MSR_GLCP_SYS_RSTPLL 0x4c000014
# define MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 (0x0000000000000002ull)
# define MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 (0x0000000000000004ull)
# define MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3 (0x0000000000000008ull)
#define MSR_GLCP_DOTPLL 0x4c000015
# define MSR_GLCP_DOTPLL_DOTRESET (0x0000000000000001ull)
# define MSR_GLCP_DOTPLL_BYPASS (0x0000000000008000ull)
# define MSR_GLCP_DOTPLL_LOCK (0x0000000002000000ull)
#endif /* !__VIDEO_GX_H__ */

3
drivers/video/i810/i810-i2c.c
View file

@ -210,8 +210,7 @@ int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid, int conn)
}
}
if (out_edid)
*out_edid = edid;
*out_edid = edid;
return (edid) ? 0 : 1;
}

32
drivers/video/imsttfb.c
View file

@ -440,9 +440,9 @@ getclkMHz(struct imstt_par *par)
static void
setclkMHz(struct imstt_par *par, __u32 MHz)
{
__u32 clk_m, clk_n, clk_p, x, stage, spilled;
__u32 clk_m, clk_n, x, stage, spilled;
clk_m = clk_n = clk_p = 0;
clk_m = clk_n = 0;
stage = spilled = 0;
for (;;) {
switch (stage) {
@ -453,7 +453,7 @@ setclkMHz(struct imstt_par *par, __u32 MHz)
clk_n++;
break;
}
x = 20 * (clk_m + 1) / ((clk_n + 1) * (clk_p ? 2 * clk_p : 1));
x = 20 * (clk_m + 1) / (clk_n + 1);
if (x == MHz)
break;
if (x > MHz) {
@ -466,7 +466,7 @@ setclkMHz(struct imstt_par *par, __u32 MHz)
par->init.pclk_m = clk_m;
par->init.pclk_n = clk_n;
par->init.pclk_p = clk_p;
par->init.pclk_p = 0;
}
static struct imstt_regvals *
@ -1372,18 +1372,24 @@ init_imstt(struct fb_info *info)
write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
write_reg_le32(par->dc_regs, SSR, 0);
/* set default values for DAC registers */
/* set default values for DAC registers */
if (par->ramdac == IBM) {
par->cmap_regs[PPMASK] = 0xff; eieio();
par->cmap_regs[PIDXHI] = 0; eieio();
for (i = 0; i < sizeof(ibm_initregs) / sizeof(*ibm_initregs); i++) {
par->cmap_regs[PIDXLO] = ibm_initregs[i].addr; eieio();
par->cmap_regs[PIDXDATA] = ibm_initregs[i].value; eieio();
par->cmap_regs[PPMASK] = 0xff;
eieio();
par->cmap_regs[PIDXHI] = 0;
eieio();
for (i = 0; i < ARRAY_SIZE(ibm_initregs); i++) {
par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
eieio();
par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
eieio();
}
} else {
for (i = 0; i < sizeof(tvp_initregs) / sizeof(*tvp_initregs); i++) {
par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr; eieio();
par->cmap_regs[TVPIDATA] = tvp_initregs[i].value; eieio();
for (i = 0; i < ARRAY_SIZE(tvp_initregs); i++) {
par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
eieio();
par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
eieio();
}
}

2
drivers/video/macmodes.c
View file

@ -380,7 +380,7 @@ int __init mac_find_mode(struct fb_var_screeninfo *var, struct fb_info *info,
if (mode_option && !strncmp(mode_option, "mac", 3)) {
mode_option += 3;
db = mac_modedb;
dbsize = sizeof(mac_modedb)/sizeof(*mac_modedb);
dbsize = ARRAY_SIZE(mac_modedb);
}
return fb_find_mode(var, info, mode_option, db, dbsize,
&mac_modedb[DEFAULT_MODEDB_INDEX], default_bpp);

2
drivers/video/matrox/matroxfb_g450.c
View file

@ -59,7 +59,7 @@ static const struct mctl g450_controls[] =
}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
};
#define G450CTRLS (sizeof(g450_controls)/sizeof(g450_controls[0]))
#define G450CTRLS ARRAY_SIZE(g450_controls)
/* Return: positive number: id found
-EINVAL: id not found, return failure

78
drivers/video/matrox/matroxfb_maven.c
View file

@ -89,12 +89,12 @@ static const struct mctl maven_controls[] =
}, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
{ { V4L2_CID_GAMMA, V4L2_CTRL_TYPE_INTEGER,
"gamma",
0, sizeof(maven_gamma)/sizeof(maven_gamma[0])-1, 1, 3,
0, ARRAY_SIZE(maven_gamma) - 1, 1, 3,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.gamma) },
{ { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
"test output",
0, 1, 1, 0,
0, 1, 1, 0,
0,
}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
{ { MATROXFB_CID_DEFLICKER, V4L2_CTRL_TYPE_INTEGER,
@ -105,7 +105,7 @@ static const struct mctl maven_controls[] =
};
#define MAVCTRLS (sizeof(maven_controls)/sizeof(maven_controls[0]))
#define MAVCTRLS ARRAY_SIZE(maven_controls)
/* Return: positive number: id found
-EINVAL: id not found, return failure
@ -129,7 +129,7 @@ static int get_ctrl_id(__u32 v4l2_id) {
struct maven_data {
struct matrox_fb_info* primary_head;
struct i2c_client* client;
struct i2c_client client;
int version;
};
@ -970,7 +970,7 @@ static inline int maven_compute_timming(struct maven_data* md,
static int maven_program_timming(struct maven_data* md,
const struct mavenregs* m) {
struct i2c_client* c = md->client;
struct i2c_client* c = &md->client;
if (m->mode == MATROXFB_OUTPUT_MODE_MONITOR) {
LR(0x80);
@ -1007,7 +1007,7 @@ static int maven_program_timming(struct maven_data* md,
}
static inline int maven_resync(struct maven_data* md) {
struct i2c_client* c = md->client;
struct i2c_client* c = &md->client;
maven_set_reg(c, 0x95, 0x20); /* start whole thing */
return 0;
}
@ -1065,48 +1065,48 @@ static int maven_set_control (struct maven_data* md,
maven_compute_bwlevel(md, &blacklevel, &whitelevel);
blacklevel = (blacklevel >> 2) | ((blacklevel & 3) << 8);
whitelevel = (whitelevel >> 2) | ((whitelevel & 3) << 8);
maven_set_reg_pair(md->client, 0x0e, blacklevel);
maven_set_reg_pair(md->client, 0x1e, whitelevel);
maven_set_reg_pair(&md->client, 0x0e, blacklevel);
maven_set_reg_pair(&md->client, 0x1e, whitelevel);
}
break;
case V4L2_CID_SATURATION:
{
maven_set_reg(md->client, 0x20, p->value);
maven_set_reg(md->client, 0x22, p->value);
maven_set_reg(&md->client, 0x20, p->value);
maven_set_reg(&md->client, 0x22, p->value);
}
break;
case V4L2_CID_HUE:
{
maven_set_reg(md->client, 0x25, p->value);
maven_set_reg(&md->client, 0x25, p->value);
}
break;
case V4L2_CID_GAMMA:
{
const struct maven_gamma* g;
g = maven_compute_gamma(md);
maven_set_reg(md->client, 0x83, g->reg83);
maven_set_reg(md->client, 0x84, g->reg84);
maven_set_reg(md->client, 0x85, g->reg85);
maven_set_reg(md->client, 0x86, g->reg86);
maven_set_reg(md->client, 0x87, g->reg87);
maven_set_reg(md->client, 0x88, g->reg88);
maven_set_reg(md->client, 0x89, g->reg89);
maven_set_reg(md->client, 0x8a, g->reg8a);
maven_set_reg(md->client, 0x8b, g->reg8b);
maven_set_reg(&md->client, 0x83, g->reg83);
maven_set_reg(&md->client, 0x84, g->reg84);
maven_set_reg(&md->client, 0x85, g->reg85);
maven_set_reg(&md->client, 0x86, g->reg86);
maven_set_reg(&md->client, 0x87, g->reg87);
maven_set_reg(&md->client, 0x88, g->reg88);
maven_set_reg(&md->client, 0x89, g->reg89);
maven_set_reg(&md->client, 0x8a, g->reg8a);
maven_set_reg(&md->client, 0x8b, g->reg8b);
}
break;
case MATROXFB_CID_TESTOUT:
{
unsigned char val
= maven_get_reg (md->client,0x8d);
= maven_get_reg(&md->client,0x8d);
if (p->value) val |= 0x10;
else val &= ~0x10;
maven_set_reg (md->client, 0x8d, val);
maven_set_reg(&md->client, 0x8d, val);
}
break;
case MATROXFB_CID_DEFLICKER:
{
maven_set_reg(md->client, 0x93, maven_compute_deflicker(md));
maven_set_reg(&md->client, 0x93, maven_compute_deflicker(md));
}
break;
}
@ -1185,7 +1185,6 @@ static int maven_init_client(struct i2c_client* clnt) {
MINFO_FROM(container_of(clnt->adapter, struct i2c_bit_adapter, adapter)->minfo);
md->primary_head = MINFO;
md->client = clnt;
down_write(&ACCESS_FBINFO(altout.lock));
ACCESS_FBINFO(outputs[1]).output = &maven_altout;
ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
@ -1243,19 +1242,17 @@ static int maven_detect_client(struct i2c_adapter* adapter, int address, int kin
I2C_FUNC_SMBUS_BYTE_DATA |
I2C_FUNC_PROTOCOL_MANGLING))
goto ERROR0;
if (!(new_client = (struct i2c_client*)kmalloc(sizeof(*new_client) + sizeof(*data),
GFP_KERNEL))) {
if (!(data = kzalloc(sizeof(*data), GFP_KERNEL))) {
err = -ENOMEM;
goto ERROR0;
}
memset(new_client, 0, sizeof(*new_client) + sizeof(*data));
data = (struct maven_data*)(new_client + 1);
new_client = &data->client;
i2c_set_clientdata(new_client, data);
new_client->addr = address;
new_client->adapter = adapter;
new_client->driver = &maven_driver;
new_client->flags = 0;
strcpy(new_client->name, "maven client");
strlcpy(new_client->name, "maven", I2C_NAME_SIZE);
if ((err = i2c_attach_client(new_client)))
goto ERROR3;
err = maven_init_client(new_client);
@ -1279,12 +1276,10 @@ static int maven_attach_adapter(struct i2c_adapter* adapter) {
static int maven_detach_client(struct i2c_client* client) {
int err;
if ((err = i2c_detach_client(client))) {
printk(KERN_ERR "maven: Cannot deregister client\n");
if ((err = i2c_detach_client(client)))
return err;
}
maven_shutdown_client(client);
kfree(client);
kfree(i2c_get_clientdata(client));
return 0;
}
@ -1297,20 +1292,13 @@ static struct i2c_driver maven_driver={
.detach_client = maven_detach_client,
};
/* ************************** */
static int matroxfb_maven_init(void) {
int err;
err = i2c_add_driver(&maven_driver);
if (err) {
printk(KERN_ERR "maven: Maven driver failed to register (%d).\n", err);
return err;
}
return 0;
static int __init matroxfb_maven_init(void)
{
return i2c_add_driver(&maven_driver);
}
static void matroxfb_maven_exit(void) {
static void __exit matroxfb_maven_exit(void)
{
i2c_del_driver(&maven_driver);
}

6
drivers/video/modedb.c
View file

@ -182,6 +182,10 @@ static const struct fb_videomode modedb[] = {
/* 1600x1200 @ 75 Hz, 93.75 kHz hsync */
NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1680x1050 @ 60 Hz, 65.191 kHz hsync */
NULL, 60, 1680, 1050, 6848, 280, 104, 30, 3, 176, 6,
FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
}, {
/* 1600x1200 @ 85 Hz, 105.77 kHz hsync */
NULL, 85, 1600, 1200, 4545, 272, 16, 37, 4, 192, 3,
@ -496,7 +500,7 @@ int fb_find_mode(struct fb_var_screeninfo *var,
/* Set up defaults */
if (!db) {
db = modedb;
dbsize = sizeof(modedb)/sizeof(*modedb);
dbsize = ARRAY_SIZE(modedb);
}
if (!default_mode)
default_mode = &modedb[DEFAULT_MODEDB_INDEX];

8
drivers/video/neofb.c
View file

@ -165,20 +165,20 @@ static int neoFindMode(int xres, int yres, int depth)
switch (depth) {
case 8:
size = sizeof(bios8) / sizeof(biosMode);
size = ARRAY_SIZE(bios8);
mode = bios8;
break;
case 16:
size = sizeof(bios16) / sizeof(biosMode);
size = ARRAY_SIZE(bios16);
mode = bios16;
break;
case 24:
size = sizeof(bios24) / sizeof(biosMode);
size = ARRAY_SIZE(bios24);
mode = bios24;
break;
#ifdef NO_32BIT_SUPPORT_YET
case 32:
size = sizeof(bios32) / sizeof(biosMode);
size = ARRAY_SIZE(bios32);
mode = bios32;
break;
#endif

12
drivers/video/nvidia/nv_accel.c
View file

@ -300,6 +300,9 @@ int nvidiafb_sync(struct fb_info *info)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
if (!par->lockup)
NVFlush(par);
@ -313,6 +316,9 @@ void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup)
return cfb_copyarea(info, region);
@ -329,6 +335,9 @@ void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
struct nvidia_par *par = info->par;
u32 color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup)
return cfb_fillrect(info, rect);
@ -412,6 +421,9 @@ void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (image->depth == 1 && !par->lockup)
nvidiafb_mono_color_expand(info, image);
else

3
drivers/video/nvidia/nv_i2c.c
View file

@ -218,8 +218,7 @@ int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
}
}
if (out_edid)
*out_edid = edid;
*out_edid = edid;
return (edid) ? 0 : 1;
}

1
drivers/video/nvidia/nv_type.h
View file

@ -129,6 +129,7 @@ struct nvidia_par {
int fpHeight;
int PanelTweak;
int paneltweak;
int pm_state;
u32 crtcSync_read;
u32 fpSyncs;
u32 dmaPut;

119
drivers/video/nvidia/nvidia.c
View file

@ -21,6 +21,7 @@
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/console.h>
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
@ -297,6 +298,8 @@ static struct pci_device_id nvidiafb_pci_tbl[] = {
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_NVIDIA, PCIE_DEVICE_ID_NVIDIA_QUADRO_NVS280,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_NVIDIA, 0x0252,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_NVIDIA, 0x0313,
@ -616,6 +619,30 @@ static int nvidia_panel_tweak(struct nvidia_par *par,
return tweak;
}
static void nvidia_vga_protect(struct nvidia_par *par, int on)
{
unsigned char tmp;
if (on) {
/*
* Turn off screen and disable sequencer.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
} else {
/*
* Reenable sequencer, then turn on screen.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
NVWriteSeq(par, 0x00, 0x03); /* End Reset */
}
}
static void nvidia_save_vga(struct nvidia_par *par,
struct _riva_hw_state *state)
{
@ -644,9 +671,9 @@ static void nvidia_save_vga(struct nvidia_par *par,
#undef DUMP_REG
static void nvidia_write_regs(struct nvidia_par *par)
static void nvidia_write_regs(struct nvidia_par *par,
struct _riva_hw_state *state)
{
struct _riva_hw_state *state = &par->ModeReg;
int i;
NVTRACE_ENTER();
@ -695,32 +722,6 @@ static void nvidia_write_regs(struct nvidia_par *par)
NVTRACE_LEAVE();
}
static void nvidia_vga_protect(struct nvidia_par *par, int on)
{
unsigned char tmp;
if (on) {
/*
* Turn off screen and disable sequencer.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */
NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */
} else {
/*
* Reenable sequencer, then turn on screen.
*/
tmp = NVReadSeq(par, 0x01);
NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */
NVWriteSeq(par, 0x00, 0x03); /* End Reset */
}
}
static int nvidia_calc_regs(struct fb_info *info)
{
struct nvidia_par *par = info->par;
@ -1069,7 +1070,8 @@ static int nvidiafb_set_par(struct fb_info *info)
nvidia_vga_protect(par, 1);
nvidia_write_regs(par);
nvidia_write_regs(par, &par->ModeReg);
NVSetStartAddress(par, 0);
#if defined (__BIG_ENDIAN)
/* turn on LFB swapping */
@ -1378,6 +1380,57 @@ static struct fb_ops nvidia_fb_ops = {
.fb_sync = nvidiafb_sync,
};
#ifdef CONFIG_PM
static int nvidiafb_suspend(struct pci_dev *dev, pm_message_t state)
{
struct fb_info *info = pci_get_drvdata(dev);
struct nvidia_par *par = info->par;
acquire_console_sem();
par->pm_state = state.event;
if (state.event == PM_EVENT_FREEZE) {
dev->dev.power.power_state = state;
} else {
fb_set_suspend(info, 1);
nvidiafb_blank(FB_BLANK_POWERDOWN, info);
nvidia_write_regs(par, &par->SavedReg);
pci_save_state(dev);
pci_disable_device(dev);
pci_set_power_state(dev, pci_choose_state(dev, state));
}
release_console_sem();
return 0;
}
static int nvidiafb_resume(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
struct nvidia_par *par = info->par;
acquire_console_sem();
pci_set_power_state(dev, PCI_D0);
if (par->pm_state != PM_EVENT_FREEZE) {
pci_restore_state(dev);
pci_enable_device(dev);
pci_set_master(dev);
}
par->pm_state = PM_EVENT_ON;
nvidiafb_set_par(info);
fb_set_suspend (info, 0);
nvidiafb_blank(FB_BLANK_UNBLANK, info);
release_console_sem();
return 0;
}
#else
#define nvidiafb_suspend NULL
#define nvidiafb_resume NULL
#endif
static int __devinit nvidia_set_fbinfo(struct fb_info *info)
{
struct fb_monspecs *specs = &info->monspecs;
@ -1721,8 +1774,6 @@ static void __exit nvidiafb_remove(struct pci_dev *pd)
struct nvidia_par *par = info->par;
NVTRACE_ENTER();
if (!info)
return;
unregister_framebuffer(info);
#ifdef CONFIG_MTRR
@ -1799,8 +1850,10 @@ static int __devinit nvidiafb_setup(char *options)
static struct pci_driver nvidiafb_driver = {
.name = "nvidiafb",
.id_table = nvidiafb_pci_tbl,
.probe = nvidiafb_probe,
.remove = __exit_p(nvidiafb_remove),
.probe = nvidiafb_probe,
.suspend = nvidiafb_suspend,
.resume = nvidiafb_resume,
.remove = __exit_p(nvidiafb_remove),
};
/* ------------------------------------------------------------------------- *

2
drivers/video/pmagb-b-fb.c
View file

@ -228,7 +228,7 @@ static void __init pmagbbfb_osc_setup(struct fb_info *info)
freq1 = (par->osc0 * count1 + count0 / 2) / count0;
par->osc1 = freq1;
for (i = 0; i < sizeof(pmagbbfb_freqs) / sizeof(*pmagbbfb_freqs); i++)
for (i = 0; i < ARRAY_SIZE(pmagbbfb_freqs); i++)
if (freq1 >= pmagbbfb_freqs[i] -
(pmagbbfb_freqs[i] + 128) / 256 &&
freq1 <= pmagbbfb_freqs[i] +

2
drivers/video/radeonfb.c
View file

@ -759,7 +759,7 @@ static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
rom = rom_base;
for (i = 0; (i < 512) && (stage != 4); i++) {
for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
for (j = 0; j < ARRAY_SIZE(radeon_sig); j++) {
if (radeon_sig[j][0] == *rom)
if (strncmp(radeon_sig[j], rom,
strlen(radeon_sig[j])) == 0) {

2
drivers/video/riva/fbdev.c
View file

@ -2073,8 +2073,6 @@ static void __exit rivafb_remove(struct pci_dev *pd)
struct riva_par *par = info->par;
NVTRACE_ENTER();
if (!info)
return;
#ifdef CONFIG_FB_RIVA_I2C
riva_delete_i2c_busses(par);

3
drivers/video/savage/savagefb-i2c.c
View file

@ -273,8 +273,7 @@ int savagefb_probe_i2c_connector(struct fb_info *info, u8 **out_edid)
}
}
if (out_edid)
*out_edid = edid;
*out_edid = edid;
return (edid) ? 0 : 1;
}

11
drivers/video/sis/init301.c
View file

@ -8564,11 +8564,9 @@ SiS_ChrontelDoSomething3(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
static void
SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr)
{
unsigned short temp,tempcl,tempch;
unsigned short temp;
SiS_LongDelay(SiS_Pr, 1);
tempcl = 3;
tempch = 0;
do {
temp = SiS_GetCH701x(SiS_Pr,0x66);
@ -8582,13 +8580,6 @@ SiS_ChrontelDoSomething2(struct SiS_Private *SiS_Pr)
SiS_SetCH701xForLCD(SiS_Pr);
if(tempcl == 0) {
if(tempch == 3) break;
SiS_ChrontelResetDB(SiS_Pr);
tempcl = 3;
tempch++;
}
tempcl--;
temp = SiS_GetCH701x(SiS_Pr,0x76);
temp &= 0xfb; /* Reset PLL */
SiS_SetCH701x(SiS_Pr,0x76,temp);

11
drivers/video/sstfb.c
View file

@ -1194,10 +1194,11 @@ static struct dac_switch dacs[] __devinitdata = {
static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
{
int i, ret = 0;
for (i=0; i<sizeof(dacs)/sizeof(dacs[0]); i++) {
for (i = 0; i < ARRAY_SIZE(dacs); i++) {
ret = dacs[i].detect(info);
if (ret) break;
if (ret)
break;
}
if (!ret)
return 0;
@ -1604,8 +1605,8 @@ static int sstfb_dump_regs(struct fb_info *info)
{FBZMODE,"fbzmode"},
};
const int pci_s = sizeof(pci_regs)/sizeof(pci_regs[0]);
const int sst_s = sizeof(sst_regs)/sizeof(sst_regs[0]);
const int pci_s = ARRAY_SIZE(pci_regs);
const int sst_s = ARRAY_SIZE(sst_regs);
struct sstfb_par *par = info->par;
struct pci_dev *dev = par->dev;
u32 pci_res[pci_s];

3
drivers/video/virgefb.c
View file

@ -616,8 +616,7 @@ static struct {
#endif
};
#define arraysize(x) (sizeof(x)/sizeof(*(x)))
#define NUM_TOTAL_MODES arraysize(virgefb_predefined)
#define NUM_TOTAL_MODES ARRAY_SIZE(virgefb_predefined)
/*
* Default to 800x600 for video=virge8:, virge16: or virge32: