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qcacmn: Replace A_TARGET_ACCESS_BEGIN/END apis

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Macros should not alter the execution of function bodies.

Change-Id: I444caccd93ec7e0fa766acce5149d0f322e837c7
CRs-Fixed: 986480
This commit is contained in:
Houston Hoffman 2016-03-14 21:11:59 -07:00 • committed by Gerrit - the friendly Code Review server
commit bac9454390
7 changed files with 43 additions and 43 deletions
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7
hif/src/ce/ce_diag.c
View file

@ -60,14 +60,17 @@ hif_dump_target_memory(struct hif_opaque_softc *hif_ctx, void *ramdump_base,
uint32_t j = 0;
u8 *temp = ramdump_base;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
while (j < size) {
val = hif_read32_mb(scn->mem + loc + j);
qdf_mem_copy(temp, &val, 4);
j += 4;
temp += 4;
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
/*
* TBDXXX: Should be a function call specific to each Target-type.

34
hif/src/ce/ce_service.c
View file

@ -1209,7 +1209,9 @@ void ce_per_engine_servicereap(struct hif_softc *scn, unsigned int ce_id)
uint32_t toeplitz_hash_result;
struct CE_state *CE_state = scn->ce_id_to_state[ce_id];
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
hif_record_ce_desc_event(scn, ce_id, HIF_CE_REAP_ENTRY,
NULL, NULL, 0);
@ -1269,7 +1271,7 @@ void ce_per_engine_servicereap(struct hif_softc *scn, unsigned int ce_id)
hif_record_ce_desc_event(scn, ce_id, HIF_CE_REAP_EXIT,
NULL, NULL, 0);
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
#endif /*ATH_11AC_TXCOMPACT */
@ -1513,7 +1515,9 @@ void ce_per_engine_service_any(int irq, struct hif_softc *scn)
int CE_id;
uint32_t intr_summary;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
if (!qdf_atomic_read(&scn->tasklet_from_intr)) {
for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
@ -1523,7 +1527,7 @@ void ce_per_engine_service_any(int irq, struct hif_softc *scn)
}
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
return;
}
@ -1539,7 +1543,7 @@ void ce_per_engine_service_any(int irq, struct hif_softc *scn)
ce_per_engine_service(scn, CE_id);
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
/*
@ -1557,7 +1561,10 @@ ce_per_engine_handler_adjust(struct CE_state *CE_state,
struct hif_softc *scn = CE_state->scn;
CE_state->disable_copy_compl_intr = disable_copy_compl_intr;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
if ((!disable_copy_compl_intr) &&
(CE_state->send_cb || CE_state->recv_cb)) {
CE_COPY_COMPLETE_INTR_ENABLE(scn, ctrl_addr);
@ -1570,8 +1577,7 @@ ce_per_engine_handler_adjust(struct CE_state *CE_state,
} else {
CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
/*Iterate the CE_state list and disable the compl interrupt
@ -1581,7 +1587,9 @@ void ce_disable_any_copy_compl_intr_nolock(struct hif_softc *scn)
{
int CE_id;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
uint32_t ctrl_addr = CE_state->ctrl_addr;
@ -1596,14 +1604,16 @@ void ce_disable_any_copy_compl_intr_nolock(struct hif_softc *scn)
CE_WATERMARK_INTR_DISABLE(scn, ctrl_addr);
}
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn)
{
int CE_id;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
for (CE_id = 0; CE_id < scn->ce_count; CE_id++) {
struct CE_state *CE_state = scn->ce_id_to_state[CE_id];
uint32_t ctrl_addr = CE_state->ctrl_addr;
@ -1622,7 +1632,7 @@ void ce_enable_any_copy_compl_intr_nolock(struct hif_softc *scn)
CE_WATERMARK_INTR_ENABLE(scn, ctrl_addr);
}
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
/**

8
hif/src/icnss_stub/icnss_stub.c
View file

@ -289,7 +289,9 @@ void icnss_dispatch_ce_irq(struct hif_softc *scn)
if (scn->hif_init_done != true)
return;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
intr_summary = CE_INTERRUPT_SUMMARY(scn);
if (intr_summary == 0) {
@ -305,10 +307,10 @@ void icnss_dispatch_ce_irq(struct hif_softc *scn)
(SOC_CORE_BASE_ADDRESS |
PCIE_INTR_ENABLE_ADDRESS));
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
return;
} else {
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
scn->ce_irq_summary = intr_summary;

5
hif/src/mp_dev.c
View file

@ -261,7 +261,8 @@ void priv_dump_agc(struct hif_softc *scn)
int i, len = 30; /* check this value for Rome and Peregrine */
uint32_t chain0, chain1, chain_mask, val;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
chain_mask =
get_target_reg_bits(scn->mem, BB_multichain_enable,
@ -305,7 +306,7 @@ void priv_dump_agc(struct hif_softc *scn)
hif_write32_mb(scn->mem + BB_gains_min_offsets,
g_priv_dump_ctx.gain_min_offsets_orig);
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
return;
}

25
hif/src/pcie/hif_io32_pci.h
View file

@ -73,13 +73,6 @@
#define CONFIG_PCIE_ENABLE_AXI_CLK_GATE 0
#if CONFIG_ATH_PCIE_MAX_PERF
#define A_TARGET_ACCESS_BEGIN(scn) \
do {struct hif_softc *unused = scn; \
unused = unused; } while (0)
#define A_TARGET_ACCESS_END(scn) \
do {struct hif_softc *unused = scn; \
unused = unused; } while (0)
#define A_TARGET_ACCESS_BEGIN_RET(scn) \
do {struct hif_softc *unused = scn; \
@ -127,12 +120,6 @@ do { \
return NULL; \
} while (0)
#define A_TARGET_ACCESS_BEGIN(scn) \
do { \
if (Q_TARGET_ACCESS_BEGIN(scn) < 0) \
return; \
} while (0)
#define A_TARGET_ACCESS_END_RET(scn) \
do { \
if (Q_TARGET_ACCESS_END(scn) < 0) \
@ -150,11 +137,6 @@ do { \
if (Q_TARGET_ACCESS_END(scn) < 0) \
return NULL; \
} while (0)
#define A_TARGET_ACCESS_END(scn) \
do { \
if (Q_TARGET_ACCESS_END(scn) < 0) \
return; \
} while (0)
#endif /* CONFIG_ATH_PCIE_MAX_PERF */
irqreturn_t hif_fw_interrupt_handler(int irq, void *arg);
@ -190,7 +172,8 @@ static inline void ce_irq_enable(struct hif_softc *scn, int ce_id)
}
}
if (scn->hif_init_done == true)
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
qdf_spin_unlock_irqrestore(&sc->irq_lock);
/* check for missed firmware crash */
@ -206,7 +189,9 @@ static inline void ce_irq_enable(struct hif_softc *scn, int ce_id)
static inline void ce_irq_disable(struct hif_softc *scn, int ce_id)
{
/* For Rome only need to wake up target */
A_TARGET_ACCESS_BEGIN(scn);
/* target access is maintained untill interrupts are re-enabled */
Q_TARGET_ACCESS_BEGIN(scn);
}
#endif /* HIF_PCI */
#endif /* __HIF_IO32_PCI_H__ */

5
hif/src/pcie/if_pci.c
View file

@ -652,7 +652,8 @@ static void hif_dump_pci_registers(struct hif_softc *scn)
uint32_t wrapper_idx[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9 };
uint32_t ce_base;
A_TARGET_ACCESS_BEGIN(scn);
if (Q_TARGET_ACCESS_BEGIN(scn) < 0)
return;
/* DEBUG_INPUT_SEL_SRC = 0x6 */
val =
@ -766,7 +767,7 @@ static void hif_dump_pci_registers(struct hif_softc *scn)
WLAN_DEBUG_OUT_OFFSET));
}
A_TARGET_ACCESS_END(scn);
Q_TARGET_ACCESS_END(scn);
}
/**

2
hif/src/snoc/hif_io32_snoc.h
View file

@ -49,8 +49,6 @@
*/
#define A_TARGET_ACCESS_BEGIN_RET_PTR(scn)
#define A_TARGET_ACCESS_END_RET_PTR(scn)
#define A_TARGET_ACCESS_BEGIN(scn)
#define A_TARGET_ACCESS_END(scn)
#define A_TARGET_ACCESS_BEGIN_RET(scn)
#define A_TARGET_ACCESS_END_RET(scn)
#define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val)