From 44bc9c82c3faa56b41dc323b997b7ef56f5f5992 Mon Sep 17 00:00:00 2001
From: Vipin Deep Kaur <vkaur@qti.qualcomm.com>
Date: Tue, 8 Sep 2020 10:24:21 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 DT nodes for shima trusted VM

Add QUPv3(Common driver, GSI and I2C) DT nodes for trusted VM
on Shima.
Assign one GPII to trusted VM by reducing one GPII from
shima primary VM set.
Assign GPII0 statically to shima touch PVM usecase.

Change-Id: Icd02eb71bf1349af73943fdf6c220d3cb0e000c8
---
 qcom/shima-qupv3.dtsi |  7 +++---
 qcom/shima-vm.dtsi    | 51 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 3 deletions(-)

diff --git a/qcom/shima-qupv3.dtsi b/qcom/shima-qupv3.dtsi
index 3c5999d267ac..aa158a9189e4 100644
--- a/qcom/shima-qupv3.dtsi
+++ b/qcom/shima-qupv3.dtsi
@@ -53,7 +53,8 @@
 			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
-		qcom,gpii-mask = <0xff>;
+		qcom,static-gpii-mask = <0x1>;
+		qcom,gpii-mask = <0x7e>;
 		qcom,ev-factor = <2>;
 		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
 		qcom,gpi-ee-offset = <0x10000>;
@@ -174,8 +175,8 @@
 		pinctrl-names = "default", "sleep";
 		pinctrl-0 = <&qupv3_se10_i2c_active>;
 		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
-		dmas = <&gpi_dma0 0 2 3 64 0>,
-			<&gpi_dma0 1 2 3 64 0>;
+		dmas = <&gpi_dma0 0 2 3 64 2>,
+			<&gpi_dma0 1 2 3 64 2>;
 		dma-names = "tx", "rx";
 		qcom,wrapper-core = <&qupv3_0>;
 		status = "disabled";
diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi
index 360c435790da..8ca6ddabf91c 100644
--- a/qcom/shima-vm.dtsi
+++ b/qcom/shima-vm.dtsi
@@ -224,5 +224,56 @@
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	/*
+	 * QUPv3 Instances
+	 * Qup0 2: SE 10
+	 */
+
+	/* QUPv3_0 wrapper instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+	};
+
+	/* GPI Instance */
+	gpi_dma0: qcom,gpi-dma@900000 {
+		compatible = "qcom,gpi-dma";
+		#dma-cells = <5>;
+		reg = <0x900000 0x60000>;
+		reg-names = "gpi-top";
+		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+		qcom,max-num-gpii = <12>;
+		qcom,gpii-mask = <0x80>;
+		qcom,ev-factor = <2>;
+		qcom,gpi-ee-offset = <0x10000>;
+		status = "ok";
+	};
+
+	/* I2C SE */
+	qupv3_se10_i2c: i2c@988000 {
+		compatible = "qcom,i2c-geni";
+		reg = <0x988000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		dmas = <&gpi_dma0 0 2 3 64 0>,
+			<&gpi_dma0 1 2 3 64 0>;
+		dma-names = "tx", "rx";
+		qcom,wrapper-core = <&qupv3_0>;
+		qcom,le-vm;
+		status = "disabled";
+	};
+
 };
 #include "shima-vm-ion.dtsi"