mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
Merge branch 'topic/asoc' into for-linus
This commit is contained in:
Takashi Iwai
commit
baf9226667
154 changed files with 8861 additions and 2350 deletions
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@ -401,6 +401,24 @@ struct twl4030_power_data {
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extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
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struct twl4030_codec_audio_data {
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unsigned int audio_mclk;
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unsigned int ramp_delay_value;
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unsigned int hs_extmute:1;
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void (*set_hs_extmute)(int mute);
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};
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struct twl4030_codec_vibra_data {
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unsigned int audio_mclk;
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unsigned int coexist;
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};
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struct twl4030_codec_data {
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unsigned int audio_mclk;
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struct twl4030_codec_audio_data *audio;
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struct twl4030_codec_vibra_data *vibra;
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};
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struct twl4030_platform_data {
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unsigned irq_base, irq_end;
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struct twl4030_bci_platform_data *bci;
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@ -409,6 +427,7 @@ struct twl4030_platform_data {
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struct twl4030_keypad_data *keypad;
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struct twl4030_usb_data *usb;
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struct twl4030_power_data *power;
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struct twl4030_codec_data *codec;
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/* LDO regulators */
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struct regulator_init_data *vdac;
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272
include/linux/mfd/twl4030-codec.h
Normal file
272
include/linux/mfd/twl4030-codec.h
Normal file
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@ -0,0 +1,272 @@
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/*
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* MFD driver for twl4030 codec submodule
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*
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* Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
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*
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* Copyright: (C) 2009 Nokia Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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||||
* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __TWL4030_CODEC_H__
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#define __TWL4030_CODEC_H__
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/* Codec registers */
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#define TWL4030_REG_CODEC_MODE 0x01
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#define TWL4030_REG_OPTION 0x02
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#define TWL4030_REG_UNKNOWN 0x03
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#define TWL4030_REG_MICBIAS_CTL 0x04
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#define TWL4030_REG_ANAMICL 0x05
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#define TWL4030_REG_ANAMICR 0x06
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#define TWL4030_REG_AVADC_CTL 0x07
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#define TWL4030_REG_ADCMICSEL 0x08
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#define TWL4030_REG_DIGMIXING 0x09
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#define TWL4030_REG_ATXL1PGA 0x0A
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#define TWL4030_REG_ATXR1PGA 0x0B
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#define TWL4030_REG_AVTXL2PGA 0x0C
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#define TWL4030_REG_AVTXR2PGA 0x0D
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#define TWL4030_REG_AUDIO_IF 0x0E
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#define TWL4030_REG_VOICE_IF 0x0F
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#define TWL4030_REG_ARXR1PGA 0x10
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#define TWL4030_REG_ARXL1PGA 0x11
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#define TWL4030_REG_ARXR2PGA 0x12
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#define TWL4030_REG_ARXL2PGA 0x13
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#define TWL4030_REG_VRXPGA 0x14
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#define TWL4030_REG_VSTPGA 0x15
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#define TWL4030_REG_VRX2ARXPGA 0x16
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#define TWL4030_REG_AVDAC_CTL 0x17
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#define TWL4030_REG_ARX2VTXPGA 0x18
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#define TWL4030_REG_ARXL1_APGA_CTL 0x19
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#define TWL4030_REG_ARXR1_APGA_CTL 0x1A
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#define TWL4030_REG_ARXL2_APGA_CTL 0x1B
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#define TWL4030_REG_ARXR2_APGA_CTL 0x1C
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#define TWL4030_REG_ATX2ARXPGA 0x1D
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#define TWL4030_REG_BT_IF 0x1E
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#define TWL4030_REG_BTPGA 0x1F
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#define TWL4030_REG_BTSTPGA 0x20
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#define TWL4030_REG_EAR_CTL 0x21
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#define TWL4030_REG_HS_SEL 0x22
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#define TWL4030_REG_HS_GAIN_SET 0x23
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#define TWL4030_REG_HS_POPN_SET 0x24
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#define TWL4030_REG_PREDL_CTL 0x25
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#define TWL4030_REG_PREDR_CTL 0x26
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#define TWL4030_REG_PRECKL_CTL 0x27
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#define TWL4030_REG_PRECKR_CTL 0x28
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#define TWL4030_REG_HFL_CTL 0x29
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#define TWL4030_REG_HFR_CTL 0x2A
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#define TWL4030_REG_ALC_CTL 0x2B
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#define TWL4030_REG_ALC_SET1 0x2C
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#define TWL4030_REG_ALC_SET2 0x2D
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#define TWL4030_REG_BOOST_CTL 0x2E
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#define TWL4030_REG_SOFTVOL_CTL 0x2F
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#define TWL4030_REG_DTMF_FREQSEL 0x30
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#define TWL4030_REG_DTMF_TONEXT1H 0x31
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#define TWL4030_REG_DTMF_TONEXT1L 0x32
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#define TWL4030_REG_DTMF_TONEXT2H 0x33
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#define TWL4030_REG_DTMF_TONEXT2L 0x34
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#define TWL4030_REG_DTMF_TONOFF 0x35
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#define TWL4030_REG_DTMF_WANONOFF 0x36
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#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37
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#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38
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#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39
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#define TWL4030_REG_APLL_CTL 0x3A
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#define TWL4030_REG_DTMF_CTL 0x3B
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#define TWL4030_REG_DTMF_PGA_CTL2 0x3C
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#define TWL4030_REG_DTMF_PGA_CTL1 0x3D
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#define TWL4030_REG_MISC_SET_1 0x3E
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#define TWL4030_REG_PCMBTMUX 0x3F
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#define TWL4030_REG_RX_PATH_SEL 0x43
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#define TWL4030_REG_VDL_APGA_CTL 0x44
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#define TWL4030_REG_VIBRA_CTL 0x45
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#define TWL4030_REG_VIBRA_SET 0x46
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#define TWL4030_REG_VIBRA_PWM_SET 0x47
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#define TWL4030_REG_ANAMIC_GAIN 0x48
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#define TWL4030_REG_MISC_SET_2 0x49
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/* Bitfield Definitions */
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/* TWL4030_CODEC_MODE (0x01) Fields */
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#define TWL4030_APLL_RATE 0xF0
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#define TWL4030_APLL_RATE_8000 0x00
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#define TWL4030_APLL_RATE_11025 0x10
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#define TWL4030_APLL_RATE_12000 0x20
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#define TWL4030_APLL_RATE_16000 0x40
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#define TWL4030_APLL_RATE_22050 0x50
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#define TWL4030_APLL_RATE_24000 0x60
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#define TWL4030_APLL_RATE_32000 0x80
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#define TWL4030_APLL_RATE_44100 0x90
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#define TWL4030_APLL_RATE_48000 0xA0
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#define TWL4030_APLL_RATE_96000 0xE0
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#define TWL4030_SEL_16K 0x08
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#define TWL4030_CODECPDZ 0x02
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#define TWL4030_OPT_MODE 0x01
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#define TWL4030_OPTION_1 (1 << 0)
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#define TWL4030_OPTION_2 (0 << 0)
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/* TWL4030_OPTION (0x02) Fields */
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#define TWL4030_ATXL1_EN (1 << 0)
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#define TWL4030_ATXR1_EN (1 << 1)
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#define TWL4030_ATXL2_VTXL_EN (1 << 2)
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#define TWL4030_ATXR2_VTXR_EN (1 << 3)
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#define TWL4030_ARXL1_VRX_EN (1 << 4)
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#define TWL4030_ARXR1_EN (1 << 5)
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#define TWL4030_ARXL2_EN (1 << 6)
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#define TWL4030_ARXR2_EN (1 << 7)
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/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
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#define TWL4030_MICBIAS2_CTL 0x40
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#define TWL4030_MICBIAS1_CTL 0x20
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#define TWL4030_HSMICBIAS_EN 0x04
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#define TWL4030_MICBIAS2_EN 0x02
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#define TWL4030_MICBIAS1_EN 0x01
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/* ANAMICL (0x05) Fields */
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#define TWL4030_CNCL_OFFSET_START 0x80
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#define TWL4030_OFFSET_CNCL_SEL 0x60
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#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00
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#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20
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#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40
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#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60
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#define TWL4030_MICAMPL_EN 0x10
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#define TWL4030_CKMIC_EN 0x08
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#define TWL4030_AUXL_EN 0x04
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#define TWL4030_HSMIC_EN 0x02
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#define TWL4030_MAINMIC_EN 0x01
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/* ANAMICR (0x06) Fields */
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#define TWL4030_MICAMPR_EN 0x10
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#define TWL4030_AUXR_EN 0x04
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#define TWL4030_SUBMIC_EN 0x01
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/* AVADC_CTL (0x07) Fields */
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#define TWL4030_ADCL_EN 0x08
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#define TWL4030_AVADC_CLK_PRIORITY 0x04
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#define TWL4030_ADCR_EN 0x02
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/* TWL4030_REG_ADCMICSEL (0x08) Fields */
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#define TWL4030_DIGMIC1_EN 0x08
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#define TWL4030_TX2IN_SEL 0x04
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#define TWL4030_DIGMIC0_EN 0x02
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#define TWL4030_TX1IN_SEL 0x01
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/* AUDIO_IF (0x0E) Fields */
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#define TWL4030_AIF_SLAVE_EN 0x80
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#define TWL4030_DATA_WIDTH 0x60
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#define TWL4030_DATA_WIDTH_16S_16W 0x00
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#define TWL4030_DATA_WIDTH_32S_16W 0x40
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#define TWL4030_DATA_WIDTH_32S_24W 0x60
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#define TWL4030_AIF_FORMAT 0x18
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#define TWL4030_AIF_FORMAT_CODEC 0x00
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#define TWL4030_AIF_FORMAT_LEFT 0x08
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#define TWL4030_AIF_FORMAT_RIGHT 0x10
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#define TWL4030_AIF_FORMAT_TDM 0x18
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#define TWL4030_AIF_TRI_EN 0x04
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#define TWL4030_CLK256FS_EN 0x02
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#define TWL4030_AIF_EN 0x01
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/* VOICE_IF (0x0F) Fields */
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#define TWL4030_VIF_SLAVE_EN 0x80
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#define TWL4030_VIF_DIN_EN 0x40
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#define TWL4030_VIF_DOUT_EN 0x20
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#define TWL4030_VIF_SWAP 0x10
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#define TWL4030_VIF_FORMAT 0x08
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#define TWL4030_VIF_TRI_EN 0x04
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#define TWL4030_VIF_SUB_EN 0x02
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#define TWL4030_VIF_EN 0x01
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/* EAR_CTL (0x21) */
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#define TWL4030_EAR_GAIN 0x30
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/* HS_GAIN_SET (0x23) Fields */
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#define TWL4030_HSR_GAIN 0x0C
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#define TWL4030_HSR_GAIN_PWR_DOWN 0x00
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#define TWL4030_HSR_GAIN_PLUS_6DB 0x04
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#define TWL4030_HSR_GAIN_0DB 0x08
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#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C
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#define TWL4030_HSL_GAIN 0x03
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#define TWL4030_HSL_GAIN_PWR_DOWN 0x00
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#define TWL4030_HSL_GAIN_PLUS_6DB 0x01
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#define TWL4030_HSL_GAIN_0DB 0x02
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#define TWL4030_HSL_GAIN_MINUS_6DB 0x03
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/* HS_POPN_SET (0x24) Fields */
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#define TWL4030_VMID_EN 0x40
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#define TWL4030_EXTMUTE 0x20
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#define TWL4030_RAMP_DELAY 0x1C
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#define TWL4030_RAMP_DELAY_20MS 0x00
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#define TWL4030_RAMP_DELAY_40MS 0x04
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#define TWL4030_RAMP_DELAY_81MS 0x08
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#define TWL4030_RAMP_DELAY_161MS 0x0C
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#define TWL4030_RAMP_DELAY_323MS 0x10
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#define TWL4030_RAMP_DELAY_645MS 0x14
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#define TWL4030_RAMP_DELAY_1291MS 0x18
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#define TWL4030_RAMP_DELAY_2581MS 0x1C
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#define TWL4030_RAMP_EN 0x02
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/* PREDL_CTL (0x25) */
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#define TWL4030_PREDL_GAIN 0x30
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/* PREDR_CTL (0x26) */
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#define TWL4030_PREDR_GAIN 0x30
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/* PRECKL_CTL (0x27) */
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#define TWL4030_PRECKL_GAIN 0x30
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/* PRECKR_CTL (0x28) */
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#define TWL4030_PRECKR_GAIN 0x30
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/* HFL_CTL (0x29, 0x2A) Fields */
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#define TWL4030_HF_CTL_HB_EN 0x04
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#define TWL4030_HF_CTL_LOOP_EN 0x08
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#define TWL4030_HF_CTL_RAMP_EN 0x10
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#define TWL4030_HF_CTL_REF_EN 0x20
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/* APLL_CTL (0x3A) Fields */
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#define TWL4030_APLL_EN 0x10
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#define TWL4030_APLL_INFREQ 0x0F
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#define TWL4030_APLL_INFREQ_19200KHZ 0x05
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#define TWL4030_APLL_INFREQ_26000KHZ 0x06
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#define TWL4030_APLL_INFREQ_38400KHZ 0x0F
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/* REG_MISC_SET_1 (0x3E) Fields */
|
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#define TWL4030_CLK64_EN 0x80
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#define TWL4030_SCRAMBLE_EN 0x40
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#define TWL4030_FMLOOP_EN 0x20
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#define TWL4030_SMOOTH_ANAVOL_EN 0x02
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#define TWL4030_DIGMIC_LR_SWAP_EN 0x01
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|
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/* VIBRA_CTL (0x45) */
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#define TWL4030_VIBRA_EN 0x01
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#define TWL4030_VIBRA_DIR 0x02
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#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2)
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#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2)
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#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2)
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#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2)
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#define TWL4030_VIBRA_SEL 0x10
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#define TWL4030_VIBRA_DIR_SEL 0x20
|
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|
||||
/* TWL4030 codec resource IDs */
|
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enum twl4030_codec_res {
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TWL4030_CODEC_RES_POWER = 0,
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TWL4030_CODEC_RES_APLL,
|
||||
TWL4030_CODEC_RES_MAX,
|
||||
};
|
||||
|
||||
int twl4030_codec_disable_resource(enum twl4030_codec_res id);
|
||||
int twl4030_codec_enable_resource(enum twl4030_codec_res id);
|
||||
unsigned int twl4030_codec_get_mclk(void);
|
||||
|
||||
#endif /* End of __TWL4030_CODEC_H__ */
|
||||
|
|
@ -30,6 +30,7 @@ struct snd_pcm_substream;
|
|||
#define SND_SOC_DAIFMT_DSP_A 3 /* L data MSB after FRM LRC */
|
||||
#define SND_SOC_DAIFMT_DSP_B 4 /* L data MSB during FRM LRC */
|
||||
#define SND_SOC_DAIFMT_AC97 5 /* AC97 */
|
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#define SND_SOC_DAIFMT_PDM 6 /* Pulse density modulation */
|
||||
|
||||
/* left and right justified also known as MSB and LSB respectively */
|
||||
#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J
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||||
|
|
@ -106,7 +107,7 @@ int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
|
|||
int div_id, int div);
|
||||
|
||||
int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
|
||||
int pll_id, unsigned int freq_in, unsigned int freq_out);
|
||||
int pll_id, int source, unsigned int freq_in, unsigned int freq_out);
|
||||
|
||||
/* Digital Audio interface formatting */
|
||||
int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
|
||||
|
|
@ -114,6 +115,10 @@ int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
|
|||
int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
|
||||
unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width);
|
||||
|
||||
int snd_soc_dai_set_channel_map(struct snd_soc_dai *dai,
|
||||
unsigned int tx_num, unsigned int *tx_slot,
|
||||
unsigned int rx_num, unsigned int *rx_slot);
|
||||
|
||||
int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate);
|
||||
|
||||
/* Digital Audio Interface mute */
|
||||
|
|
@ -136,8 +141,8 @@ struct snd_soc_dai_ops {
|
|||
*/
|
||||
int (*set_sysclk)(struct snd_soc_dai *dai,
|
||||
int clk_id, unsigned int freq, int dir);
|
||||
int (*set_pll)(struct snd_soc_dai *dai,
|
||||
int pll_id, unsigned int freq_in, unsigned int freq_out);
|
||||
int (*set_pll)(struct snd_soc_dai *dai, int pll_id, int source,
|
||||
unsigned int freq_in, unsigned int freq_out);
|
||||
int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
|
||||
|
||||
/*
|
||||
|
|
@ -148,6 +153,9 @@ struct snd_soc_dai_ops {
|
|||
int (*set_tdm_slot)(struct snd_soc_dai *dai,
|
||||
unsigned int tx_mask, unsigned int rx_mask,
|
||||
int slots, int slot_width);
|
||||
int (*set_channel_map)(struct snd_soc_dai *dai,
|
||||
unsigned int tx_num, unsigned int *tx_slot,
|
||||
unsigned int rx_num, unsigned int *rx_slot);
|
||||
int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -206,6 +206,12 @@
|
|||
.get = snd_soc_dapm_get_enum_double, \
|
||||
.put = snd_soc_dapm_put_enum_double, \
|
||||
.private_value = (unsigned long)&xenum }
|
||||
#define SOC_DAPM_ENUM_VIRT(xname, xenum) \
|
||||
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
|
||||
.info = snd_soc_info_enum_double, \
|
||||
.get = snd_soc_dapm_get_enum_virt, \
|
||||
.put = snd_soc_dapm_put_enum_virt, \
|
||||
.private_value = (unsigned long)&xenum }
|
||||
#define SOC_DAPM_VALUE_ENUM(xname, xenum) \
|
||||
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
|
||||
.info = snd_soc_info_enum_double, \
|
||||
|
|
@ -260,6 +266,10 @@ int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol,
|
|||
struct snd_ctl_elem_value *ucontrol);
|
||||
int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol);
|
||||
int snd_soc_dapm_get_enum_virt(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol);
|
||||
int snd_soc_dapm_put_enum_virt(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol);
|
||||
int snd_soc_dapm_get_value_enum_double(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol);
|
||||
int snd_soc_dapm_put_value_enum_double(struct snd_kcontrol *kcontrol,
|
||||
|
|
@ -333,6 +343,10 @@ struct snd_soc_dapm_route {
|
|||
const char *sink;
|
||||
const char *control;
|
||||
const char *source;
|
||||
|
||||
/* Note: currently only supported for links where source is a supply */
|
||||
int (*connected)(struct snd_soc_dapm_widget *source,
|
||||
struct snd_soc_dapm_widget *sink);
|
||||
};
|
||||
|
||||
/* dapm audio path between two widgets */
|
||||
|
|
@ -349,6 +363,9 @@ struct snd_soc_dapm_path {
|
|||
u32 connect:1; /* source and sink widgets are connected */
|
||||
u32 walked:1; /* path has been walked */
|
||||
|
||||
int (*connected)(struct snd_soc_dapm_widget *source,
|
||||
struct snd_soc_dapm_widget *sink);
|
||||
|
||||
struct list_head list_source;
|
||||
struct list_head list_sink;
|
||||
struct list_head list;
|
||||
|
|
|
|||
|
|
@ -223,15 +223,15 @@ int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
|
|||
int addr_bits, int data_bits,
|
||||
enum snd_soc_control_type control);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
int snd_soc_suspend_device(struct device *dev);
|
||||
int snd_soc_resume_device(struct device *dev);
|
||||
#endif
|
||||
|
||||
/* pcm <-> DAI connect */
|
||||
void snd_soc_free_pcms(struct snd_soc_device *socdev);
|
||||
int snd_soc_new_pcms(struct snd_soc_device *socdev, int idx, const char *xid);
|
||||
int snd_soc_init_card(struct snd_soc_device *socdev);
|
||||
|
||||
/* Utility functions to get clock rates from various things */
|
||||
int snd_soc_calc_frame_size(int sample_size, int channels, int tdm_slots);
|
||||
int snd_soc_params_to_frame_size(struct snd_pcm_hw_params *params);
|
||||
int snd_soc_calc_bclk(int fs, int sample_size, int channels, int tdm_slots);
|
||||
int snd_soc_params_to_bclk(struct snd_pcm_hw_params *parms);
|
||||
|
||||
/* set runtime hw params */
|
||||
int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream,
|
||||
|
|
@ -333,6 +333,8 @@ struct snd_soc_jack_gpio {
|
|||
int debounce_time;
|
||||
struct snd_soc_jack *jack;
|
||||
struct work_struct work;
|
||||
|
||||
int (*jack_status_check)(void);
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
@ -413,6 +415,7 @@ struct snd_soc_codec {
|
|||
unsigned int num_dai;
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *debugfs_codec_root;
|
||||
struct dentry *debugfs_reg;
|
||||
struct dentry *debugfs_pop_time;
|
||||
struct dentry *debugfs_dapm;
|
||||
|
|
|
|||
20
include/sound/tlv320dac33-plat.h
Normal file
20
include/sound/tlv320dac33-plat.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Platform header for Texas Instruments TLV320DAC33 codec driver
|
||||
*
|
||||
* Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
|
||||
*
|
||||
* Copyright: (C) 2009 Nokia Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __TLV320DAC33_PLAT_H
|
||||
#define __TLV320DAC33_PLAT_H
|
||||
|
||||
struct tlv320dac33_platform_data {
|
||||
int power_gpio;
|
||||
};
|
||||
|
||||
#endif /* __TLV320DAC33_PLAT_H */
|
||||
30
include/sound/tpa6130a2-plat.h
Normal file
30
include/sound/tpa6130a2-plat.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* TPA6130A2 driver platform header
|
||||
*
|
||||
* Copyright (C) Nokia Corporation
|
||||
*
|
||||
* Written by Peter Ujfalusi <peter.ujfalusi@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
|
||||
* 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef TPA6130A2_PLAT_H
|
||||
#define TPA6130A2_PLAT_H
|
||||
|
||||
struct tpa6130a2_platform_data {
|
||||
int power_gpio;
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue