From bb7d5f490f4c9271ecb28411b4aab8e9c8b76c00 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 8 Jul 2020 18:58:51 +0530 Subject: [PATCH] disp: msm: sde: add rev check for shima target Add required revision checks for shima target. Change-Id: I610263844c280e12b91a8b88781a6b6344415174 Signed-off-by: Krishna Manikandan --- msm/sde/sde_hw_catalog.c | 22 ++++++++++++++++++++++ msm/sde/sde_hw_catalog.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 1ccf71f04dfa..7f602644ecde 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -4748,6 +4748,28 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_sui_blendstage = true; sde_cfg->vbif_disable_inner_outer_shareable = true; sde_cfg->mdss_hw_block_size = 0x158; + } else if (IS_SHIMA_TARGET(hw_rev)) { + sde_cfg->has_cwb_support = true; + sde_cfg->has_wb_ubwc = true; + sde_cfg->has_qsync = true; + sde_cfg->perf.min_prefill_lines = 35; + sde_cfg->vbif_qos_nlvl = 8; + sde_cfg->ts_prefill_rev = 2; + sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; + sde_cfg->delay_prg_fetch_start = true; + sde_cfg->sui_ns_allowed = true; + sde_cfg->sui_misr_supported = true; + sde_cfg->sui_block_xin_mask = 0xE71; + sde_cfg->has_sui_blendstage = true; + sde_cfg->has_3d_merge_reset = true; + sde_cfg->has_hdr = true; + sde_cfg->has_hdr_plus = true; + set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features); + sde_cfg->has_vig_p010 = true; + sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0; + sde_cfg->inline_disable_const_clr = true; + sde_cfg->vbif_disable_inner_outer_shareable = true; + sde_cfg->mdss_hw_block_size = 0x158; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index 11d4b8bf11ef..800675f8dd67 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -44,6 +44,7 @@ #define SDE_HW_VER_630 SDE_HW_VER(6, 3, 0) /* bengal */ #define SDE_HW_VER_700 SDE_HW_VER(7, 0, 0) /* lahaina */ #define SDE_HW_VER_660 SDE_HW_VER(6, 6, 0) /* holi */ +#define SDE_HW_VER_670 SDE_HW_VER(6, 7, 0) /* shima */ /* Avoid using below IS_XXX macros outside catalog, use feature bit instead */ #define IS_SDE_MAJOR_SAME(rev1, rev2) \ @@ -65,6 +66,7 @@ #define IS_BENGAL_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_630) #define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700) #define IS_HOLI_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_660) +#define IS_SHIMA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_670) #define SDE_HW_BLK_NAME_LEN 16