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ARM: late Exynos multiplatform changes

Browse source 
These continue the multiplatform support for exynos, adding support
 for building most of the essential drivers (clocksource, clk, irqchip)
 when combined with other platforms. As a result, it should become
 really easy to add full multiplatform exynos support in 3.11, although
 we don't yet enable it for 3.10.
 
 The changes were not included in the earlier multiplatform series
 in order to avoid clashes with the other Exynos updates.
 
 This also includes work from Tomasz Figa to fix the pwm clocksource
 code on Exynos, which is not strictly required for multiplatform,
 but related to the other patches in this set and needed as a bug
 fix for at least one board.
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Merge tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull late ARM Exynos multiplatform changes from Arnd Bergmann:
 "These continue the multiplatform support for exynos, adding support
  for building most of the essential drivers (clocksource, clk, irqchip)
  when combined with other platforms.  As a result, it should become
  really easy to add full multiplatform exynos support in 3.11, although
  we don't yet enable it for 3.10.

  The changes were not included in the earlier multiplatform series in
  order to avoid clashes with the other Exynos updates.

  This also includes work from Tomasz Figa to fix the pwm clocksource
  code on Exynos, which is not strictly required for multiplatform, but
  related to the other patches in this set and needed as a bug fix for
  at least one board."

* tag 'multiplatform-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (22 commits)
  ARM: dts: exynops4210: really add universal_c210 dts
  ARM: dts: exynos4210: Add basic dts file for universal_c210 board
  ARM: dts: exynos4: Add node for PWM device
  ARM: SAMSUNG: Do not register legacy timer interrupts on Exynos
  clocksource: samsung_pwm_timer: Work around rounding errors in clockevents core
  clocksource: samsung_pwm_timer: Correct programming of clock events
  clocksource: samsung_pwm_timer: Use proper clockevents max_delta
  clocksource: samsung_pwm_timer: Add support for non-DT platforms
  clocksource: samsung_pwm_timer: Drop unused samsung_pwm struct
  clocksource: samsung_pwm_timer: Keep all driver data in a structure
  clocksource: samsung_pwm_timer: Make PWM spinlock global
  clocksource: samsung_pwm_timer: Let platforms select the driver
  Documentation: Add device tree bindings for Samsung PWM timers
  clocksource: add samsung pwm timer driver
  irqchip: exynos: look up irq using irq_find_mapping
  irqchip: exynos: pass irq_base from platform
  irqchip: exynos: localize irq lookup for ATAGS
  irqchip: exynos: allocate combiner_data dynamically
  irqchip: exynos: pass max combiner number to combiner_init
  ARM: exynos: add missing properties for combiner IRQs
  ...
This commit is contained in:
Linus Torvalds 2013-05-07 11:28:42 -07:00
commit bb9055b274
20 changed files with 1098 additions and 154 deletions
Download patch file Download diff file Expand all files Collapse all files

93
drivers/clk/samsung/clk-exynos4.c
View file

@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <plat/cpu.h>
#include "clk.h"
#include "clk-pll.h"
@ -910,16 +909,6 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
CLK_IGNORE_UNUSED, 0),
};
#ifdef CONFIG_OF
static struct of_device_id exynos4_clk_ids[] __initdata = {
{ .compatible = "samsung,exynos4210-clock",
.data = (void *)EXYNOS4210, },
{ .compatible = "samsung,exynos4412-clock",
.data = (void *)EXYNOS4X12, },
{ },
};
#endif
/*
* The parent of the fin_pll clock is selected by the XOM[0] bit. This bit
* resides in chipid register space, outside of the clock controller memory
@ -927,33 +916,40 @@ static struct of_device_id exynos4_clk_ids[] __initdata = {
* controller is first remapped and the value of XOM[0] bit is read to
* determine the parent clock.
*/
static void __init exynos4_clk_register_finpll(void)
static unsigned long exynos4_get_xom(void)
{
struct samsung_fixed_rate_clock fclk;
unsigned long xom = 0;
void __iomem *chipid_base;
struct device_node *np;
struct clk *clk;
void __iomem *chipid_base = S5P_VA_CHIPID;
unsigned long xom, finpll_f = 24000000;
char *parent_name;
np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
if (np)
if (np) {
chipid_base = of_iomap(np, 0);
if (chipid_base) {
xom = readl(chipid_base + 8);
parent_name = xom & 1 ? "xusbxti" : "xxti";
clk = clk_get(NULL, parent_name);
if (IS_ERR(clk)) {
pr_err("%s: failed to lookup parent clock %s, assuming "
"fin_pll clock frequency is 24MHz\n", __func__,
parent_name);
} else {
finpll_f = clk_get_rate(clk);
}
if (chipid_base)
xom = readl(chipid_base + 8);
iounmap(chipid_base);
}
return xom;
}
static void __init exynos4_clk_register_finpll(unsigned long xom)
{
struct samsung_fixed_rate_clock fclk;
struct clk *clk;
unsigned long finpll_f = 24000000;
char *parent_name;
parent_name = xom & 1 ? "xusbxti" : "xxti";
clk = clk_get(NULL, parent_name);
if (IS_ERR(clk)) {
pr_err("%s: failed to lookup parent clock %s, assuming "
"fin_pll clock frequency is 24MHz\n", __func__,
parent_name);
} else {
pr_err("%s: failed to map chipid registers, assuming "
"fin_pll clock frequency is 24MHz\n", __func__);
finpll_f = clk_get_rate(clk);
}
fclk.id = fin_pll;
@ -963,8 +959,6 @@ static void __init exynos4_clk_register_finpll(void)
fclk.fixed_rate = finpll_f;
samsung_clk_register_fixed_rate(&fclk, 1);
if (np)
iounmap(chipid_base);
}
/*
@ -988,28 +982,14 @@ static __initdata struct of_device_id ext_clk_match[] = {
};
/* register exynos4 clocks */
void __init exynos4_clk_init(struct device_node *np)
void __init exynos4_clk_init(struct device_node *np, enum exynos4_soc exynos4_soc, void __iomem *reg_base, unsigned long xom)
{
void __iomem *reg_base;
struct clk *apll, *mpll, *epll, *vpll;
u32 exynos4_soc;
if (np) {
const struct of_device_id *match;
match = of_match_node(exynos4_clk_ids, np);
exynos4_soc = (u32)match->data;
reg_base = of_iomap(np, 0);
if (!reg_base)
panic("%s: failed to map registers\n", __func__);
} else {
reg_base = S5P_VA_CMU;
if (soc_is_exynos4210())
exynos4_soc = EXYNOS4210;
else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4_soc = EXYNOS4X12;
else
panic("%s: unable to determine soc\n", __func__);
}
if (exynos4_soc == EXYNOS4210)
@ -1026,7 +1006,7 @@ void __init exynos4_clk_init(struct device_node *np)
ARRAY_SIZE(exynos4_fixed_rate_ext_clks),
ext_clk_match);
exynos4_clk_register_finpll();
exynos4_clk_register_finpll(xom);
if (exynos4_soc == EXYNOS4210) {
apll = samsung_clk_register_pll45xx("fout_apll", "fin_pll",
@ -1087,5 +1067,16 @@ void __init exynos4_clk_init(struct device_node *np)
_get_rate("sclk_epll"), _get_rate("sclk_vpll"),
_get_rate("arm_clk"));
}
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4_clk_init);
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4_clk_init);
static void __init exynos4210_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4210, NULL, exynos4_get_xom());
}
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
static void __init exynos4412_clk_init(struct device_node *np)
{
exynos4_clk_init(np, EXYNOS4X12, NULL, exynos4_get_xom());
}
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);

1
drivers/clk/samsung/clk-exynos5250.c
View file

@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <plat/cpu.h>
#include "clk.h"
#include "clk-pll.h"

1
drivers/clk/samsung/clk-exynos5440.c
View file

@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <plat/cpu.h>
#include "clk.h"
#include "clk-pll.h"

2
drivers/clk/samsung/clk.h
View file

@ -20,8 +20,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <mach/map.h>
/**
* struct samsung_clock_alias: information about mux clock
* @id: platform specific id of the clock.