mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-09 21:59:12 -04:00
Merge "ASoC: change OUT_DIR to PRODUCT_OUT for wcd9360"
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commit
bbb2154a37
15 changed files with 14237 additions and 3 deletions
|
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@ -29,3 +29,8 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codec
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include $(MY_LOCAL_PATH)/asoc/codecs/sdm660_cdc/Android.mk
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include $(MY_LOCAL_PATH)/asoc/codecs/msm_sdw/Android.mk
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endif
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ifeq ($(call is-board-platform-in-list,msmnile),true)
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$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd9360/Module.symvers)
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include $(MY_LOCAL_PATH)/asoc/codecs/wcd9360/Android.mk
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endif
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|
|
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|||
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@ -1,4 +1,4 @@
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/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2011-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -105,6 +105,8 @@
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#define IS_CODEC_VERSION(wcd, wcdversion) \
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((wcd->version == wcdversion) ? true : false)
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#define PAHU_VERSION_1_0 0
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enum {
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CDC_V_1_0,
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CDC_V_1_1,
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|
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License version 2 and
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@ -126,6 +126,106 @@ static int msm_cdc_check_supply_param(struct device *dev,
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return 0;
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}
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/*
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* msm_cdc_disable_ondemand_supply:
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* Disable codec ondemand supply
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*
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* @dev: pointer to codec device
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* @supplies: pointer to regulator bulk data
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* @cdc_vreg: pointer to platform regulator data
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* @num_supplies: number of supplies
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* @supply_name: Ondemand supply name to be enabled
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*
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* Return error code if supply disable is failed
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*/
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int msm_cdc_disable_ondemand_supply(struct device *dev,
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struct regulator_bulk_data *supplies,
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struct cdc_regulator *cdc_vreg,
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int num_supplies,
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char *supply_name)
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{
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int rc, i;
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if ((!supply_name) || (!supplies)) {
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pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
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__func__);
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return -EINVAL;
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}
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/* input parameter validation */
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rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
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if (rc)
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return rc;
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for (i = 0; i < num_supplies; i++) {
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if (cdc_vreg[i].ondemand &&
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!strcmp(cdc_vreg[i].name, supply_name)) {
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rc = regulator_disable(supplies[i].consumer);
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if (rc)
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dev_err(dev, "%s: failed to disable supply %s, err:%d\n",
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__func__, supplies[i].supply, rc);
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break;
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}
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}
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if (i == num_supplies) {
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dev_err(dev, "%s: not able to find supply %s\n",
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__func__, supply_name);
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rc = -EINVAL;
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}
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return rc;
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}
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EXPORT_SYMBOL(msm_cdc_disable_ondemand_supply);
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/*
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* msm_cdc_enable_ondemand_supply:
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* Enable codec ondemand supply
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*
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* @dev: pointer to codec device
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* @supplies: pointer to regulator bulk data
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* @cdc_vreg: pointer to platform regulator data
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* @num_supplies: number of supplies
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* @supply_name: Ondemand supply name to be enabled
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*
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* Return error code if supply enable is failed
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*/
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int msm_cdc_enable_ondemand_supply(struct device *dev,
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struct regulator_bulk_data *supplies,
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struct cdc_regulator *cdc_vreg,
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int num_supplies,
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char *supply_name)
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{
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int rc, i;
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if ((!supply_name) || (!supplies)) {
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pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
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__func__);
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return -EINVAL;
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}
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/* input parameter validation */
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rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
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if (rc)
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return rc;
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for (i = 0; i < num_supplies; i++) {
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if (cdc_vreg[i].ondemand &&
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!strcmp(cdc_vreg[i].name, supply_name)) {
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rc = regulator_enable(supplies[i].consumer);
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if (rc)
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dev_err(dev, "%s: failed to enable supply %s, rc: %d\n",
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__func__, supplies[i].supply, rc);
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break;
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}
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}
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if (i == num_supplies) {
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dev_err(dev, "%s: not able to find supply %s\n",
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__func__, supply_name);
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rc = -EINVAL;
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}
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return rc;
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}
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EXPORT_SYMBOL(msm_cdc_enable_ondemand_supply);
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/*
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* msm_cdc_disable_static_supplies:
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* Disable codec static supplies
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@ -1,4 +1,4 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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/* Copyright (c) 2016, 2018 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -29,6 +29,14 @@ struct cdc_regulator {
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extern int msm_cdc_get_power_supplies(struct device *dev,
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struct cdc_regulator **cdc_vreg,
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int *total_num_supplies);
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extern int msm_cdc_disable_ondemand_supply(struct device *dev,
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struct regulator_bulk_data *supplies,
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struct cdc_regulator *cdc_vreg,
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int num_supplies, char *supply_name);
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extern int msm_cdc_enable_ondemand_supply(struct device *dev,
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struct regulator_bulk_data *supplies,
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struct cdc_regulator *cdc_vreg,
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int num_supplies, char *supply_name);
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extern int msm_cdc_disable_static_supplies(struct device *dev,
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struct regulator_bulk_data *supplies,
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struct cdc_regulator *cdc_vreg,
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50
asoc/codecs/wcd9360/Android.mk
Normal file
50
asoc/codecs/wcd9360/Android.mk
Normal file
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@ -0,0 +1,50 @@
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# Android makefile for audio kernel modules
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# Assume no targets will be supported
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# Check if this driver needs be built for current target
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ifeq ($(call is-board-platform,msmnile),true)
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AUDIO_SELECT := CONFIG_SND_SOC_SDM855=m
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endif
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AUDIO_CHIPSET := audio
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# Build/Package only in case of supported target
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ifeq ($(call is-board-platform-in-list,msmnile),true)
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LOCAL_PATH := $(call my-dir)
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# This makefile is only for DLKM
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ifneq ($(findstring vendor,$(LOCAL_PATH)),)
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ifneq ($(findstring opensource,$(LOCAL_PATH)),)
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AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/vendor/qcom/opensource/audio-kernel
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endif # opensource
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DLKM_DIR := $(TOP)/device/qcom/common/dlkm
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# Build audio.ko as $(AUDIO_CHIPSET)_audio.ko
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###########################################################
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# This is set once per LOCAL_PATH, not per (kernel) module
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KBUILD_OPTIONS := AUDIO_ROOT=$(AUDIO_BLD_DIR)
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# We are actually building audio.ko here, as per the
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# requirement we are specifying <chipset>_audio.ko as LOCAL_MODULE.
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# This means we need to rename the module to <chipset>_audio.ko
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# after audio.ko is built.
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KBUILD_OPTIONS += MODNAME=wcd9360_dlkm
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KBUILD_OPTIONS += BOARD_PLATFORM=$(TARGET_BOARD_PLATFORM)
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KBUILD_OPTIONS += $(AUDIO_SELECT)
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###########################################################
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include $(CLEAR_VARS)
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LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9360.ko
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LOCAL_MODULE_KBUILD_NAME := wcd9360_dlkm.ko
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LOCAL_MODULE_TAGS := optional
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LOCAL_MODULE_DEBUG_ENABLE := true
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LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT)
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include $(DLKM_DIR)/AndroidKernelModule.mk
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###########################################################
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###########################################################
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endif # DLKM check
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endif # supported target check
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104
asoc/codecs/wcd9360/Kbuild
Normal file
104
asoc/codecs/wcd9360/Kbuild
Normal file
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@ -0,0 +1,104 @@
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# We can build either as part of a standalone Kernel build or as
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# an external module. Determine which mechanism is being used
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ifeq ($(MODNAME),)
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KERNEL_BUILD := 1
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else
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KERNEL_BUILD := 0
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endif
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ifeq ($(KERNEL_BUILD), 1)
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# These are configurable via Kconfig for kernel-based builds
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# Need to explicitly configure for Android-based builds
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AUDIO_BLD_DIR := $(ANDROID_BUILD_TOP)/kernel/msm-4.14
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AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
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endif
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ifeq ($(KERNEL_BUILD), 0)
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ifeq ($(CONFIG_ARCH_SDM855), y)
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include $(AUDIO_ROOT)/config/sdm855auto.conf
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export
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INCS += -include $(AUDIO_ROOT)/config/sdm855autoconf.h
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endif
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endif
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# As per target team, build is done as follows:
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# Defconfig : build with default flags
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# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
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# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
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# Perf : Using appropriate msmXXXX-perf_defconfig
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#
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# Shipment builds (user variants) should not have any debug feature
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# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
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# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
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# there is no other way to identify defconfig builds, QTI internal
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# representation of perf builds (identified using the string 'perf'),
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# is used to identify if the build is a slub or defconfig one. This
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# way no critical debug feature will be enabled for perf and shipment
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# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
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# config.
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############ UAPI ############
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UAPI_DIR := uapi
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UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
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############ COMMON ############
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COMMON_DIR := include
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COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
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############ WCD934X ############
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# for WCD9360 Codec
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ifdef CONFIG_SND_SOC_WCD9360
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WCD9360_OBJS += wcd9360.o
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WCD9360_OBJS += wcd9360-dsp-cntl.o
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endif
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LINUX_INC += -Iinclude/linux
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INCS += $(COMMON_INC) \
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$(UAPI_INC)
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EXTRA_CFLAGS += $(INCS)
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|
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|
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CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
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-DANI_LITTLE_BIT_ENDIAN \
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-DDOT11F_LITTLE_ENDIAN_HOST \
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-DANI_COMPILER_TYPE_GCC \
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-DANI_OS_TYPE_ANDROID=6 \
|
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-DPTT_SOCK_SVC_ENABLE \
|
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-Wall\
|
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-Werror\
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-D__linux__
|
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|
||||
KBUILD_CPPFLAGS += $(CDEFINES)
|
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|
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# Currently, for versions of gcc which support it, the kernel Makefile
|
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# is disabling the maybe-uninitialized warning. Re-enable it for the
|
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# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
|
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# will override the kernel settings.
|
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ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
|
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EXTRA_CFLAGS += -Wmaybe-uninitialized
|
||||
endif
|
||||
#EXTRA_CFLAGS += -Wmissing-prototypes
|
||||
|
||||
ifeq ($(call cc-option-yn, -Wheader-guard),y)
|
||||
EXTRA_CFLAGS += -Wheader-guard
|
||||
endif
|
||||
|
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ifeq ($(KERNEL_BUILD), 0)
|
||||
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers
|
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KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/Module.symvers
|
||||
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers
|
||||
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers
|
||||
KBUILD_EXTRA_SYMBOLS +=$(OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers
|
||||
endif
|
||||
|
||||
# Module information used by KBuild framework
|
||||
obj-$(CONFIG_SND_SOC_WCD9360) += wcd9360_dlkm.o
|
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wcd9360_dlkm-y := $(WCD9360_OBJS)
|
||||
|
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# inject some build related information
|
||||
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"
|
||||
2231
asoc/codecs/wcd9360/wcd9360-defaults.h
Normal file
2231
asoc/codecs/wcd9360/wcd9360-defaults.h
Normal file
File diff suppressed because it is too large
Load diff
1354
asoc/codecs/wcd9360/wcd9360-dsp-cntl.c
Normal file
1354
asoc/codecs/wcd9360/wcd9360-dsp-cntl.c
Normal file
File diff suppressed because it is too large
Load diff
120
asoc/codecs/wcd9360/wcd9360-dsp-cntl.h
Normal file
120
asoc/codecs/wcd9360/wcd9360-dsp-cntl.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __WCD9360_DSP_CNTL_H__
|
||||
#define __WCD9360_DSP_CNTL_H__
|
||||
|
||||
#include <linux/miscdevice.h>
|
||||
#include <sound/soc.h>
|
||||
#include <sound/wcd-dsp-mgr.h>
|
||||
|
||||
enum cdc_ssr_event {
|
||||
WCD_CDC_DOWN_EVENT,
|
||||
WCD_CDC_UP_EVENT,
|
||||
};
|
||||
|
||||
struct wcd_dsp_cdc_cb {
|
||||
/* Callback to enable codec clock */
|
||||
int (*cdc_clk_en)(struct snd_soc_codec *, bool);
|
||||
/* Callback to vote and unvote for SVS2 mode */
|
||||
void (*cdc_vote_svs)(struct snd_soc_codec *, bool);
|
||||
};
|
||||
|
||||
struct wcd_dsp_irq_info {
|
||||
/* IPC interrupt */
|
||||
int cpe_ipc1_irq;
|
||||
|
||||
/* CPE error summary interrupt */
|
||||
int cpe_err_irq;
|
||||
|
||||
/*
|
||||
* Bit mask to indicate which of the
|
||||
* error interrupts are to be considered
|
||||
* as fatal.
|
||||
*/
|
||||
u16 fatal_irqs;
|
||||
};
|
||||
|
||||
struct wcd_dsp_params {
|
||||
struct wcd_dsp_cdc_cb *cb;
|
||||
struct wcd_dsp_irq_info irqs;
|
||||
|
||||
/* Rate at which the codec clock operates */
|
||||
u32 clk_rate;
|
||||
|
||||
/*
|
||||
* Represents the dsp instance, will be used
|
||||
* to create sysfs and debugfs entries with
|
||||
* directory wdsp<dsp-instance>
|
||||
*/
|
||||
u32 dsp_instance;
|
||||
};
|
||||
|
||||
struct wdsp_ssr_entry {
|
||||
u8 offline;
|
||||
u8 offline_change;
|
||||
wait_queue_head_t offline_poll_wait;
|
||||
struct snd_info_entry *entry;
|
||||
};
|
||||
|
||||
struct wcd_dsp_cntl {
|
||||
/* Handle to codec */
|
||||
struct snd_soc_codec *codec;
|
||||
|
||||
/* Clk rate of the codec clock */
|
||||
u32 clk_rate;
|
||||
|
||||
/* Callbacks to codec driver */
|
||||
const struct wcd_dsp_cdc_cb *cdc_cb;
|
||||
|
||||
/* Completion to indicate WDSP boot done */
|
||||
struct completion boot_complete;
|
||||
|
||||
struct wcd_dsp_irq_info irqs;
|
||||
u32 dsp_instance;
|
||||
|
||||
/* Sysfs entries related */
|
||||
int boot_reqs;
|
||||
struct kobject wcd_kobj;
|
||||
|
||||
/* Debugfs related */
|
||||
struct dentry *entry;
|
||||
u32 debug_mode;
|
||||
bool ramdump_enable;
|
||||
|
||||
/* WDSP manager drivers data */
|
||||
struct device *m_dev;
|
||||
struct wdsp_mgr_ops *m_ops;
|
||||
|
||||
/* clk related */
|
||||
struct mutex clk_mutex;
|
||||
bool is_clk_enabled;
|
||||
|
||||
/* Keep track of WDSP boot status */
|
||||
bool is_wdsp_booted;
|
||||
|
||||
/* SSR related */
|
||||
struct wdsp_ssr_entry ssr_entry;
|
||||
struct mutex ssr_mutex;
|
||||
|
||||
/* Misc device related */
|
||||
char miscdev_name[256];
|
||||
struct miscdevice miscdev;
|
||||
};
|
||||
|
||||
void wcd9360_dsp_cntl_init(struct snd_soc_codec *codec,
|
||||
struct wcd_dsp_params *params,
|
||||
struct wcd_dsp_cntl **cntl);
|
||||
void wcd9360_dsp_cntl_deinit(struct wcd_dsp_cntl **cntl);
|
||||
int wcd9360_dsp_ssr_event(struct wcd_dsp_cntl *cntl, enum cdc_ssr_event event);
|
||||
#endif /* end __WCD_DSP_CONTROL_H__ */
|
||||
56
asoc/codecs/wcd9360/wcd9360-irq.h
Normal file
56
asoc/codecs/wcd9360/wcd9360-irq.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __WCD9360_IRQ_H_
|
||||
#define __WCD9360_IRQ_H_
|
||||
|
||||
enum {
|
||||
/* INTR_REG 0 */
|
||||
WCD9360_IRQ_MISC = 1,
|
||||
WCD9360_IRQ_RESERVED_0,
|
||||
WCD9360_IRQ_LDO_RXTX_SCD,
|
||||
WCD9360_IRQ_EAR_PA_SCD,
|
||||
WCD9360_IRQ_AUX_PA_SCD,
|
||||
WCD9360_IRQ_AUX_PA_CNP_COMPLETE,
|
||||
WCD9360_IRQ_EAR_PA_CNP_COMPLETE,
|
||||
/* INTR_REG 1 */
|
||||
WCD9360_IRQ_RESERVED_1,
|
||||
WCD9360_IRQ_RESERVED_2,
|
||||
WCD9360_IRQ_RESERVED_3,
|
||||
WCD9360_IRQ_RESERVED_4,
|
||||
WCD9360_IRQ_RESERVED_5,
|
||||
WCD9360_IRQ_RESERVED_6,
|
||||
WCD9360_IRQ_RESERVED_7,
|
||||
WCD9360_IRQ_RESERVED_8,
|
||||
/* INTR_REG 2 */
|
||||
WCD9360_IRQ_RESERVED_9,
|
||||
WCD9360_IRQ_RESERVED_10,
|
||||
WCD9360_IRQ_RESERVED_11,
|
||||
WCD9360_IRQ_RESERVED_12,
|
||||
WCD9360_IRQ_SOUNDWIRE,
|
||||
WCD9360_IRQ_RESERVED_13,
|
||||
WCD9360_IRQ_RCO_ERROR,
|
||||
WCD9360_IRQ_CPE_ERROR,
|
||||
/* INTR_REG 3 */
|
||||
WCD9360_IRQ_MAD_AUDIO,
|
||||
WCD9360_IRQ_MAD_BEACON,
|
||||
WCD9360_IRQ_MAD_ULTRASOUND,
|
||||
WCD9360_IRQ_RESERVED_14,
|
||||
WCD9360_IRQ_RESERVED_15,
|
||||
WCD9360_IRQ_CPE1_INTR,
|
||||
WCD9360_IRQ_CPE2_INTR,
|
||||
WCD9360_IRQ_CPE_LPASS_ACK,
|
||||
WCD9360_NUM_IRQS,
|
||||
};
|
||||
|
||||
#endif
|
||||
110
asoc/codecs/wcd9360/wcd9360-regmap.c
Normal file
110
asoc/codecs/wcd9360/wcd9360-regmap.c
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/device.h>
|
||||
#include <asoc/wcd9360-registers.h>
|
||||
#include "../core.h"
|
||||
#include "../wcd9xxx-regmap.h"
|
||||
#include "wcd9360-defaults.h"
|
||||
|
||||
static bool wcd9360_is_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
u8 pg_num, reg_offset;
|
||||
const u8 *reg_tbl = NULL;
|
||||
|
||||
/*
|
||||
* Get the page number from MSB of codec register. If its 0x80, assign
|
||||
* the corresponding page index PAGE_0x80.
|
||||
*/
|
||||
pg_num = reg >> 8;
|
||||
if (pg_num == 128)
|
||||
pg_num = WCD9360_PAGE_128;
|
||||
else if (pg_num == 80)
|
||||
pg_num = WCD9360_PAGE_80;
|
||||
else if (pg_num > 15)
|
||||
return false;
|
||||
|
||||
reg_tbl = wcd9360_reg[pg_num];
|
||||
reg_offset = reg & 0xFF;
|
||||
|
||||
if (reg_tbl && reg_tbl[reg_offset])
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool wcd9360_is_volatile_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
u8 pg_num, reg_offset;
|
||||
const u8 *reg_tbl = NULL;
|
||||
|
||||
pg_num = reg >> 8;
|
||||
|
||||
if (pg_num == 1 || pg_num == 2 ||
|
||||
pg_num == 6 || pg_num == 7)
|
||||
return true;
|
||||
else if (pg_num == 128)
|
||||
pg_num = WCD9360_PAGE_128;
|
||||
else if (pg_num == 80)
|
||||
pg_num = WCD9360_PAGE_80;
|
||||
else if (pg_num > 15)
|
||||
return false;
|
||||
|
||||
reg_tbl = wcd9360_reg[pg_num];
|
||||
reg_offset = reg & 0xFF;
|
||||
|
||||
if (reg_tbl && reg_tbl[reg_offset] == WCD9360_RO)
|
||||
return true;
|
||||
|
||||
if ((reg >= WCD9360_CODEC_RPM_RST_CTL) &&
|
||||
(reg <= WCD9360_CHIP_TIER_CTRL_ALT_FUNC_EN))
|
||||
return true;
|
||||
|
||||
if ((reg >= WCD9360_CDC_ANC0_IIR_COEFF_1_CTL) &&
|
||||
(reg <= WCD9360_CDC_ANC0_FB_GAIN_CTL))
|
||||
return true;
|
||||
|
||||
if ((reg >= WCD9360_CODEC_CPR_WR_DATA_0) &&
|
||||
(reg <= WCD9360_CODEC_CPR_RD_DATA_3))
|
||||
return true;
|
||||
|
||||
/*
|
||||
* Need to mark volatile for registers that are writable but
|
||||
* only few bits are read-only
|
||||
*/
|
||||
switch (reg) {
|
||||
case WCD9360_CODEC_RPM_CLK_BYPASS:
|
||||
case WCD9360_CODEC_RPM_CLK_GATE:
|
||||
case WCD9360_CODEC_RPM_CLK_MCLK_CFG:
|
||||
case WCD9360_CODEC_CPR_SVS_CX_VDD:
|
||||
case WCD9360_CODEC_CPR_SVS2_CX_VDD:
|
||||
case WCD9360_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL:
|
||||
case WCD9360_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL:
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
struct regmap_config wcd9360_regmap_config = {
|
||||
.reg_bits = 16,
|
||||
.val_bits = 8,
|
||||
.cache_type = REGCACHE_RBTREE,
|
||||
.reg_defaults = wcd9360_defaults,
|
||||
.num_reg_defaults = ARRAY_SIZE(wcd9360_defaults),
|
||||
.max_register = WCD9360_MAX_REGISTER,
|
||||
.volatile_reg = wcd9360_is_volatile_register,
|
||||
.readable_reg = wcd9360_is_readable_register,
|
||||
.can_multi_write = true,
|
||||
};
|
||||
864
asoc/codecs/wcd9360/wcd9360-routing.h
Normal file
864
asoc/codecs/wcd9360/wcd9360-routing.h
Normal file
|
|
@ -0,0 +1,864 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __WCD9360_ROUTING_H__
|
||||
#define __WCD9360_ROUTING_H__
|
||||
|
||||
#include <sound/soc-dapm.h>
|
||||
|
||||
const struct snd_soc_dapm_route pahu_slim_audio_map[] = {
|
||||
|
||||
{"AIF4 MAD", NULL, "AIF4_MAD Mixer"},
|
||||
|
||||
/* Virtual input widget Mixer SLIMBUS */
|
||||
{"AIF1_CAP Mixer", "SLIM TX0", "SLIM TX0"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX1", "SLIM TX1"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX2", "SLIM TX2"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX3", "SLIM TX3"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX4", "SLIM TX4"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX5", "SLIM TX5"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX6", "SLIM TX6"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX7", "SLIM TX7"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX8", "SLIM TX8"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX9", "SLIM TX9"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX10", "SLIM TX10"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX11", "SLIM TX11"},
|
||||
{"AIF1_CAP Mixer", "SLIM TX13", "SLIM TX13"},
|
||||
|
||||
{"AIF2_CAP Mixer", "SLIM TX0", "SLIM TX0"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX1", "SLIM TX1"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX2", "SLIM TX2"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX3", "SLIM TX3"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX4", "SLIM TX4"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX5", "SLIM TX5"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX6", "SLIM TX6"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX7", "SLIM TX7"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX8", "SLIM TX8"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX9", "SLIM TX9"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX10", "SLIM TX10"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX11", "SLIM TX11"},
|
||||
{"AIF2_CAP Mixer", "SLIM TX13", "SLIM TX13"},
|
||||
|
||||
{"AIF3_CAP Mixer", "SLIM TX0", "SLIM TX0"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX1", "SLIM TX1"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX2", "SLIM TX2"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX3", "SLIM TX3"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX4", "SLIM TX4"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX5", "SLIM TX5"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX6", "SLIM TX6"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX7", "SLIM TX7"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX8", "SLIM TX8"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX9", "SLIM TX9"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX10", "SLIM TX10"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX11", "SLIM TX11"},
|
||||
{"AIF3_CAP Mixer", "SLIM TX13", "SLIM TX13"},
|
||||
|
||||
{"AIF4_MAD Mixer", "SLIM TX13", "SLIM TX13"},
|
||||
|
||||
/* CDC Tx interface with SLIMBUS */
|
||||
{"SLIM TX0", NULL, "CDC_IF TX0 MUX"},
|
||||
{"SLIM TX1", NULL, "CDC_IF TX1 MUX"},
|
||||
{"SLIM TX2", NULL, "CDC_IF TX2 MUX"},
|
||||
{"SLIM TX3", NULL, "CDC_IF TX3 MUX"},
|
||||
{"SLIM TX4", NULL, "CDC_IF TX4 MUX"},
|
||||
{"SLIM TX5", NULL, "CDC_IF TX5 MUX"},
|
||||
{"SLIM TX6", NULL, "CDC_IF TX6 MUX"},
|
||||
{"SLIM TX7", NULL, "CDC_IF TX7 MUX"},
|
||||
{"SLIM TX8", NULL, "CDC_IF TX8 MUX"},
|
||||
{"SLIM TX9", NULL, "CDC_IF TX9 MUX"},
|
||||
{"SLIM TX10", NULL, "CDC_IF TX10 MUX"},
|
||||
{"SLIM TX11", NULL, "CDC_IF TX11 MUX"},
|
||||
{"SLIM TX13", NULL, "CDC_IF TX13 MUX"},
|
||||
|
||||
{"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
{"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
|
||||
|
||||
{"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
{"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
|
||||
|
||||
{"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
{"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
|
||||
|
||||
{"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
{"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
|
||||
|
||||
{"SLIM RX0", NULL, "SLIM RX0 MUX"},
|
||||
{"SLIM RX1", NULL, "SLIM RX1 MUX"},
|
||||
{"SLIM RX2", NULL, "SLIM RX2 MUX"},
|
||||
{"SLIM RX3", NULL, "SLIM RX3 MUX"},
|
||||
{"SLIM RX4", NULL, "SLIM RX4 MUX"},
|
||||
{"SLIM RX5", NULL, "SLIM RX5 MUX"},
|
||||
{"SLIM RX6", NULL, "SLIM RX6 MUX"},
|
||||
{"SLIM RX7", NULL, "SLIM RX7 MUX"},
|
||||
|
||||
/* CDC Rx interface with SLIMBUS */
|
||||
{"CDC_IF RX0 MUX", "SLIM RX0", "SLIM RX0"},
|
||||
{"CDC_IF RX1 MUX", "SLIM RX1", "SLIM RX1"},
|
||||
{"CDC_IF RX2 MUX", "SLIM RX2", "SLIM RX2"},
|
||||
{"CDC_IF RX3 MUX", "SLIM RX3", "SLIM RX3"},
|
||||
{"CDC_IF RX4 MUX", "SLIM RX4", "SLIM RX4"},
|
||||
{"CDC_IF RX5 MUX", "SLIM RX5", "SLIM RX5"},
|
||||
{"CDC_IF RX6 MUX", "SLIM RX6", "SLIM RX6"},
|
||||
{"CDC_IF RX7 MUX", "SLIM RX7", "SLIM RX7"},
|
||||
|
||||
/* VI Feedback */
|
||||
{"AIF4_VI Mixer", "SPKR_VI_1", "VIINPUT"},
|
||||
{"AIF4_VI Mixer", "SPKR_VI_2", "VIINPUT"},
|
||||
{"AIF4 VI", NULL, "AIF4_VI Mixer"},
|
||||
|
||||
};
|
||||
|
||||
const struct snd_soc_dapm_route pahu_audio_map[] = {
|
||||
|
||||
/* Virtual input widgets */
|
||||
{"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
|
||||
{"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
|
||||
{"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
|
||||
|
||||
/* WDMA3 */
|
||||
{"WDMA3 PORT0 MUX", "DEC0", "ADC MUX0"},
|
||||
{"WDMA3 PORT0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
|
||||
{"WDMA3 PORT1 MUX", "DEC1", "ADC MUX1"},
|
||||
{"WDMA3 PORT1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
|
||||
{"WDMA3 PORT2 MUX", "DEC2", "ADC MUX2"},
|
||||
{"WDMA3 PORT2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
|
||||
{"WDMA3 PORT3 MUX", "DEC3", "ADC MUX3"},
|
||||
{"WDMA3 PORT3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
|
||||
{"WDMA3 PORT4 MUX", "DEC4", "ADC MUX4"},
|
||||
{"WDMA3 PORT4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
|
||||
{"WDMA3 PORT5 MUX", "DEC5", "ADC MUX5"},
|
||||
{"WDMA3 PORT5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
|
||||
{"WDMA3 PORT6 MUX", "DEC6", "ADC MUX6"},
|
||||
{"WDMA3 PORT6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
|
||||
|
||||
{"WDMA3 CH0 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
|
||||
{"WDMA3 CH0 MUX", "PORT_7", "ADC MUX7"},
|
||||
{"WDMA3 CH0 MUX", "PORT_8", "ADC MUX8"},
|
||||
|
||||
{"WDMA3 CH1 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
|
||||
{"WDMA3 CH1 MUX", "PORT_7", "ADC MUX7"},
|
||||
{"WDMA3 CH1 MUX", "PORT_8", "ADC MUX8"},
|
||||
|
||||
{"WDMA3 CH2 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
|
||||
{"WDMA3 CH2 MUX", "PORT_7", "ADC MUX7"},
|
||||
{"WDMA3 CH2 MUX", "PORT_8", "ADC MUX8"},
|
||||
|
||||
{"WDMA3 CH3 MUX", "PORT_0", "WDMA3 PORT0 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_1", "WDMA3 PORT1 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_2", "WDMA3 PORT2 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_3", "WDMA3 PORT3 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_4", "WDMA3 PORT4 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_5", "WDMA3 PORT5 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_6", "WDMA3 PORT6 MUX"},
|
||||
{"WDMA3 CH3 MUX", "PORT_7", "ADC MUX7"},
|
||||
{"WDMA3 CH3 MUX", "PORT_8", "ADC MUX8"},
|
||||
|
||||
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH0 MUX"},
|
||||
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH1 MUX"},
|
||||
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH2 MUX"},
|
||||
{"WDMA3_CH_MIXER", NULL, "WDMA3 CH3 MUX"},
|
||||
|
||||
{"WDMA3_ON_OFF", "Switch", "WDMA3_CH_MIXER"},
|
||||
{"WDMA3_OUT", NULL, "WDMA3_ON_OFF"},
|
||||
|
||||
/* MAD */
|
||||
{"MAD_SEL MUX", "SPE", "MAD_CPE_INPUT"},
|
||||
{"MAD_SEL MUX", "MSM", "MADINPUT"},
|
||||
|
||||
{"MAD_INP MUX", "MAD", "MAD_SEL MUX"},
|
||||
{"MAD_INP MUX", "DEC1", "ADC MUX1"},
|
||||
|
||||
{"MAD_BROADCAST", "Switch", "MAD_INP MUX"},
|
||||
{"MAD_CPE1", "Switch", "MAD_INP MUX"},
|
||||
{"MAD_CPE2", "Switch", "MAD_INP MUX"},
|
||||
|
||||
{"MAD_CPE_OUT1", NULL, "MAD_CPE1"},
|
||||
{"MAD_CPE_OUT2", NULL, "MAD_CPE2"},
|
||||
|
||||
{"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
|
||||
{"CDC_IF TX0 MUX", "RX_MIX_TX0", "RX MIX TX0 MUX"},
|
||||
{"CDC_IF TX0 MUX", "DEC0_192", "ADC US MUX0"},
|
||||
|
||||
{"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
|
||||
{"CDC_IF TX1 MUX", "RX_MIX_TX1", "RX MIX TX1 MUX"},
|
||||
{"CDC_IF TX1 MUX", "DEC1_192", "ADC US MUX1"},
|
||||
|
||||
{"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
|
||||
{"CDC_IF TX2 MUX", "RX_MIX_TX2", "RX MIX TX2 MUX"},
|
||||
{"CDC_IF TX2 MUX", "DEC2_192", "ADC US MUX2"},
|
||||
|
||||
{"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
|
||||
{"CDC_IF TX3 MUX", "RX_MIX_TX3", "RX MIX TX3 MUX"},
|
||||
{"CDC_IF TX3 MUX", "DEC3_192", "ADC US MUX3"},
|
||||
|
||||
{"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
|
||||
{"CDC_IF TX4 MUX", "RX_MIX_TX4", "RX MIX TX4 MUX"},
|
||||
{"CDC_IF TX4 MUX", "DEC4_192", "ADC US MUX4"},
|
||||
|
||||
{"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
|
||||
{"CDC_IF TX5 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
|
||||
{"CDC_IF TX5 MUX", "DEC5_192", "ADC US MUX5"},
|
||||
|
||||
{"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
|
||||
{"CDC_IF TX6 MUX", "RX_MIX_TX6", "RX MIX TX6 MUX"},
|
||||
{"CDC_IF TX6 MUX", "DEC6_192", "ADC US MUX6"},
|
||||
|
||||
{"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
|
||||
{"CDC_IF TX7 MUX", "RX_MIX_TX7", "RX MIX TX7 MUX"},
|
||||
{"CDC_IF TX7 MUX", "DEC7_192", "ADC US MUX7"},
|
||||
|
||||
{"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
|
||||
{"CDC_IF TX8 MUX", "RX_MIX_TX8", "RX MIX TX8 MUX"},
|
||||
{"CDC_IF TX8 MUX", "DEC8_192", "ADC US MUX8"},
|
||||
|
||||
{"CDC_IF TX9 MUX", "DEC7", "ADC MUX7"},
|
||||
{"CDC_IF TX9 MUX", "DEC7_192", "ADC US MUX7"},
|
||||
{"CDC_IF TX10 MUX", "DEC6", "ADC MUX6"},
|
||||
{"CDC_IF TX10 MUX", "DEC6_192", "ADC US MUX6"},
|
||||
|
||||
{"CDC_IF TX11 MUX", "DEC_0_5", "CDC_IF TX11 INP1 MUX"},
|
||||
{"CDC_IF TX11 MUX", "DEC_9_12", "CDC_IF TX11 INP1 MUX"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC0", "ADC MUX0"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC1", "ADC MUX1"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC2", "ADC MUX2"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC3", "ADC MUX3"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC4", "ADC MUX4"},
|
||||
{"CDC_IF TX11 INP1 MUX", "DEC5", "ADC MUX5"},
|
||||
{"CDC_IF TX11 INP1 MUX", "RX_MIX_TX5", "RX MIX TX5 MUX"},
|
||||
|
||||
{"CDC_IF TX13 MUX", "MAD_BRDCST", "MAD_BROADCAST"},
|
||||
{"CDC_IF TX13 MUX", "CDC_DEC_5", "CDC_IF TX13 INP1 MUX"},
|
||||
{"CDC_IF TX13 INP1 MUX", "DEC5", "ADC MUX5"},
|
||||
{"CDC_IF TX13 INP1 MUX", "DEC5_192", "ADC US MUX5"},
|
||||
|
||||
{"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX0 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX0 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX0 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX1 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX1 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX1 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX2 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX2 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX2 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX3 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX3 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX3 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX3 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX4 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX4 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX4 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX4 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX5 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX5 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX5 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX5 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX6 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX6 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX6 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX6 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX7 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX7 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX7 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX7 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"RX MIX TX8 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
|
||||
{"RX MIX TX8 MUX", "RX_MIX7", "RX INT7 SEC MIX"},
|
||||
{"RX MIX TX8 MUX", "RX_MIX8", "RX INT8 SEC MIX"},
|
||||
{"RX MIX TX8 MUX", "RX_MIX9", "RX INT9 SEC MIX"},
|
||||
|
||||
{"ADC US MUX0", "US_Switch", "ADC MUX0"},
|
||||
{"ADC US MUX1", "US_Switch", "ADC MUX1"},
|
||||
{"ADC US MUX2", "US_Switch", "ADC MUX2"},
|
||||
{"ADC US MUX3", "US_Switch", "ADC MUX3"},
|
||||
{"ADC US MUX4", "US_Switch", "ADC MUX4"},
|
||||
{"ADC US MUX5", "US_Switch", "ADC MUX5"},
|
||||
{"ADC US MUX6", "US_Switch", "ADC MUX6"},
|
||||
{"ADC US MUX7", "US_Switch", "ADC MUX7"},
|
||||
{"ADC US MUX8", "US_Switch", "ADC MUX8"},
|
||||
|
||||
{"ADC MUX0", "DMIC", "DMIC MUX0"},
|
||||
{"ADC MUX0", "AMIC", "AMIC MUX0"},
|
||||
{"ADC MUX1", "DMIC", "DMIC MUX1"},
|
||||
{"ADC MUX1", "AMIC", "AMIC MUX1"},
|
||||
{"ADC MUX2", "DMIC", "DMIC MUX2"},
|
||||
{"ADC MUX2", "AMIC", "AMIC MUX2"},
|
||||
{"ADC MUX3", "DMIC", "DMIC MUX3"},
|
||||
{"ADC MUX3", "AMIC", "AMIC MUX3"},
|
||||
{"ADC MUX4", "DMIC", "DMIC MUX4"},
|
||||
{"ADC MUX4", "AMIC", "AMIC MUX4"},
|
||||
{"ADC MUX5", "DMIC", "DMIC MUX5"},
|
||||
{"ADC MUX5", "AMIC", "AMIC MUX5"},
|
||||
{"ADC MUX6", "DMIC", "DMIC MUX6"},
|
||||
{"ADC MUX6", "AMIC", "AMIC MUX6"},
|
||||
{"ADC MUX7", "DMIC", "DMIC MUX7"},
|
||||
{"ADC MUX7", "AMIC", "AMIC MUX7"},
|
||||
{"ADC MUX8", "DMIC", "DMIC MUX8"},
|
||||
{"ADC MUX8", "AMIC", "AMIC MUX8"},
|
||||
{"ADC MUX10", "DMIC", "DMIC MUX10"},
|
||||
{"ADC MUX10", "AMIC", "AMIC MUX10"},
|
||||
{"ADC MUX11", "DMIC", "DMIC MUX11"},
|
||||
{"ADC MUX11", "AMIC", "AMIC MUX11"},
|
||||
|
||||
{"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX0", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX1", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX2", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX3", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX4", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX5", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX6", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX7", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
{"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX10"},
|
||||
{"ADC MUX8", "ANC_FB_TUNE1", "ADC MUX11"},
|
||||
|
||||
{"DMIC MUX0", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX0", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX0", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX0", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX0", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX0", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX0", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX0", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX0", "ADC1", "ADC1"},
|
||||
{"AMIC MUX0", "ADC2", "ADC2"},
|
||||
{"AMIC MUX0", "ADC3", "ADC3"},
|
||||
{"AMIC MUX0", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX1", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX1", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX1", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX1", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX1", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX1", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX1", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX1", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX1", "ADC1", "ADC1"},
|
||||
{"AMIC MUX1", "ADC2", "ADC2"},
|
||||
{"AMIC MUX1", "ADC3", "ADC3"},
|
||||
{"AMIC MUX1", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX2", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX2", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX2", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX2", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX2", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX2", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX2", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX2", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX2", "ADC1", "ADC1"},
|
||||
{"AMIC MUX2", "ADC2", "ADC2"},
|
||||
{"AMIC MUX2", "ADC3", "ADC3"},
|
||||
{"AMIC MUX2", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX3", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX3", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX3", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX3", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX3", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX3", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX3", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX3", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX3", "ADC1", "ADC1"},
|
||||
{"AMIC MUX3", "ADC2", "ADC2"},
|
||||
{"AMIC MUX3", "ADC3", "ADC3"},
|
||||
{"AMIC MUX3", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX4", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX4", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX4", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX4", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX4", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX4", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX4", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX4", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX4", "ADC1", "ADC1"},
|
||||
{"AMIC MUX4", "ADC2", "ADC2"},
|
||||
{"AMIC MUX4", "ADC3", "ADC3"},
|
||||
{"AMIC MUX4", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX5", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX5", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX5", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX5", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX5", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX5", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX5", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX5", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX5", "ADC1", "ADC1"},
|
||||
{"AMIC MUX5", "ADC2", "ADC2"},
|
||||
{"AMIC MUX5", "ADC3", "ADC3"},
|
||||
{"AMIC MUX5", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX6", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX6", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX6", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX6", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX6", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX6", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX6", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX6", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX6", "ADC1", "ADC1"},
|
||||
{"AMIC MUX6", "ADC2", "ADC2"},
|
||||
{"AMIC MUX6", "ADC3", "ADC3"},
|
||||
{"AMIC MUX6", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX7", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX7", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX7", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX7", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX7", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX7", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX7", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX7", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX7", "ADC1", "ADC1"},
|
||||
{"AMIC MUX7", "ADC2", "ADC2"},
|
||||
{"AMIC MUX7", "ADC3", "ADC3"},
|
||||
{"AMIC MUX7", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX8", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX8", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX8", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX8", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX8", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX8", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX8", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX8", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX8", "ADC1", "ADC1"},
|
||||
{"AMIC MUX8", "ADC2", "ADC2"},
|
||||
{"AMIC MUX8", "ADC3", "ADC3"},
|
||||
{"AMIC MUX8", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX10", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX10", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX10", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX10", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX10", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX10", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX10", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX10", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX10", "ADC1", "ADC1"},
|
||||
{"AMIC MUX10", "ADC2", "ADC2"},
|
||||
{"AMIC MUX10", "ADC3", "ADC3"},
|
||||
{"AMIC MUX10", "ADC4", "ADC4"},
|
||||
|
||||
{"DMIC MUX11", "DMIC0", "DMIC0"},
|
||||
{"DMIC MUX11", "DMIC1", "DMIC1"},
|
||||
{"DMIC MUX11", "DMIC2", "DMIC2"},
|
||||
{"DMIC MUX11", "DMIC3", "DMIC3"},
|
||||
{"DMIC MUX11", "DMIC4", "DMIC4"},
|
||||
{"DMIC MUX11", "DMIC5", "DMIC5"},
|
||||
{"DMIC MUX11", "DMIC6", "DMIC6"},
|
||||
{"DMIC MUX11", "DMIC7", "DMIC7"},
|
||||
{"AMIC MUX11", "ADC1", "ADC1"},
|
||||
{"AMIC MUX11", "ADC2", "ADC2"},
|
||||
{"AMIC MUX11", "ADC3", "ADC3"},
|
||||
{"AMIC MUX11", "ADC4", "ADC4"},
|
||||
|
||||
{"ADC2_IN", "AMIC1", "AMIC1"},
|
||||
{"ADC2_IN", "AMIC2", "AMIC2"},
|
||||
{"ADC4_IN", "AMIC3", "AMIC3"},
|
||||
{"ADC4_IN", "AMIC4", "AMIC4"},
|
||||
|
||||
{"ADC1", NULL, "AMIC1"},
|
||||
{"ADC2", NULL, "ADC2_IN"},
|
||||
{"ADC3", NULL, "AMIC3"},
|
||||
{"ADC4", NULL, "ADC4_IN"},
|
||||
|
||||
{"ADC1", NULL, "LDO_RXTX"},
|
||||
{"ADC2", NULL, "LDO_RXTX"},
|
||||
{"ADC3", NULL, "LDO_RXTX"},
|
||||
{"ADC4", NULL, "LDO_RXTX"},
|
||||
|
||||
{"RX INT0_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
|
||||
|
||||
{"RX INT7_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT7_1 MIX1 INP0", "IIR0", "IIR0"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT7_1 MIX1 INP1", "IIR0", "IIR0"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT7_1 MIX1 INP2", "IIR0", "IIR0"},
|
||||
|
||||
{"RX INT8_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT8_1 MIX1 INP0", "IIR0", "IIR0"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT8_1 MIX1 INP1", "IIR0", "IIR0"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT8_1 MIX1 INP2", "IIR0", "IIR0"},
|
||||
|
||||
{"RX INT9_1 MIX1 INP0", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT9_1 MIX1 INP0", "IIR0", "IIR0"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT9_1 MIX1 INP1", "IIR0", "IIR0"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT9_1 MIX1 INP2", "IIR0", "IIR0"},
|
||||
|
||||
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
|
||||
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
|
||||
{"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
|
||||
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP0"},
|
||||
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP1"},
|
||||
{"RX INT7_1 MIX1", NULL, "RX INT7_1 MIX1 INP2"},
|
||||
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP0"},
|
||||
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP1"},
|
||||
{"RX INT8_1 MIX1", NULL, "RX INT8_1 MIX1 INP2"},
|
||||
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP0"},
|
||||
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP1"},
|
||||
{"RX INT9_1 MIX1", NULL, "RX INT9_1 MIX1 INP2"},
|
||||
|
||||
/* Mixing path INT0 */
|
||||
{"RX INT0_2 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT0_2 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT0_2 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT0_2 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT0_2 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT0_2 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT0_2 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT0_2 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
|
||||
{"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
|
||||
|
||||
/* Mixing path INT7 */
|
||||
{"RX INT7_2 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT7_2 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT7_2 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT7_2 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT7_2 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT7_2 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT7_2 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT7_2 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT7_2 INTERP", NULL, "RX INT7_2 MUX"},
|
||||
{"RX INT7 SEC MIX", NULL, "RX INT7_2 INTERP"},
|
||||
|
||||
/* Mixing path INT8 */
|
||||
{"RX INT8_2 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT8_2 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT8_2 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT8_2 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT8_2 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT8_2 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT8_2 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT8_2 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT8_2 INTERP", NULL, "RX INT8_2 MUX"},
|
||||
{"RX INT8 SEC MIX", NULL, "RX INT8_2 INTERP"},
|
||||
|
||||
/* Mixing path INT9 */
|
||||
{"RX INT9_2 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"RX INT9_2 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"RX INT9_2 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"RX INT9_2 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"RX INT9_2 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"RX INT9_2 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"RX INT9_2 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"RX INT9_2 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"RX INT9_2 INTERP", NULL, "RX INT9_2 MUX"},
|
||||
{"RX INT9 SEC MIX", NULL, "RX INT9_2 INTERP"},
|
||||
|
||||
{"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
|
||||
{"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
|
||||
{"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
|
||||
{"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
|
||||
{"RX INT0 DEM MUX", NULL, "RX INT0 MIX2"},
|
||||
{"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
|
||||
{"RX INT0 DAC", NULL, "LDO_RXTX"},
|
||||
{"EAR PA", NULL, "RX INT0 DAC"},
|
||||
{"EAR", NULL, "EAR PA"},
|
||||
|
||||
{"RX INT7_1 INTERP", NULL, "RX INT7_1 MIX1"},
|
||||
{"RX INT7 SEC MIX", NULL, "RX INT7_1 INTERP"},
|
||||
{"RX INT7 MIX2", NULL, "RX INT7 SEC MIX"},
|
||||
{"RX INT7 MIX2", NULL, "RX INT7 MIX2 INP"},
|
||||
{"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
|
||||
{"SPK1 OUT", NULL, "RX INT7 CHAIN"},
|
||||
|
||||
{"RX INT8_1 INTERP", NULL, "RX INT8_1 MIX1"},
|
||||
{"RX INT8 SEC MIX", NULL, "RX INT8_1 INTERP"},
|
||||
{"RX INT8 SEC MIX", NULL, "RX INT8_1 MIX1"},
|
||||
{"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
|
||||
{"SPK2 OUT", NULL, "RX INT8 CHAIN"},
|
||||
|
||||
{"RX INT9_1 INTERP", NULL, "RX INT9_1 MIX1"},
|
||||
{"RX INT9 SEC MIX", NULL, "RX INT9_1 INTERP"},
|
||||
{"RX INT9 MIX2", NULL, "RX INT9 SEC MIX"},
|
||||
{"RX INT9 MIX2", NULL, "RX INT9 MIX2 INP"},
|
||||
{"RX INT9 DEM MUX", NULL, "RX INT9 MIX2"},
|
||||
{"RX INT9 DAC", NULL, "RX INT9 DEM MUX"},
|
||||
{"RX INT9 DAC", NULL, "LDO_RXTX"},
|
||||
{"AUX PA", NULL, "RX INT9 DAC"},
|
||||
{"AUX", NULL, "AUX PA"},
|
||||
|
||||
/* ANC Routing */
|
||||
{"ANC0 FB MUX", "ANC_IN_EAR", "RX INT0 MIX2"},
|
||||
{"ANC0 FB MUX", "ANC_IN_EAR_SPKR", "RX INT7 MIX2"},
|
||||
|
||||
{"ANC OUT EAR Enable", "Switch", "ADC MUX10"},
|
||||
{"ANC OUT EAR Enable", "Switch", "ADC MUX11"},
|
||||
{"RX INT0 MIX2", NULL, "ANC OUT EAR Enable"},
|
||||
|
||||
{"ANC EAR PA", NULL, "RX INT0 DAC"},
|
||||
{"ANC EAR", NULL, "ANC EAR PA"},
|
||||
|
||||
{"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX10"},
|
||||
{"ANC OUT EAR SPKR Enable", "Switch", "ADC MUX11"},
|
||||
{"RX INT7 MIX2", NULL, "ANC OUT EAR SPKR Enable"},
|
||||
|
||||
{"ANC SPKR PA Enable", "Switch", "RX INT7 CHAIN"},
|
||||
{"ANC SPK1 PA", NULL, "ANC SPKR PA Enable"},
|
||||
{"SPK1 OUT", NULL, "ANC SPK1 PA"},
|
||||
|
||||
/*
|
||||
* SRC0 input to Sidetone RX Mixer
|
||||
* on RX0, RX1, RX2, RX3, RX4 and RX7 chains
|
||||
*/
|
||||
{"IIR0", NULL, "IIR0 INP0 MUX"},
|
||||
{"IIR0 INP0 MUX", "DEC0", "ADC MUX0"},
|
||||
{"IIR0 INP0 MUX", "DEC1", "ADC MUX1"},
|
||||
{"IIR0 INP0 MUX", "DEC2", "ADC MUX2"},
|
||||
{"IIR0 INP0 MUX", "DEC3", "ADC MUX3"},
|
||||
{"IIR0 INP0 MUX", "DEC4", "ADC MUX4"},
|
||||
{"IIR0 INP0 MUX", "DEC5", "ADC MUX5"},
|
||||
{"IIR0 INP0 MUX", "DEC6", "ADC MUX6"},
|
||||
{"IIR0 INP0 MUX", "DEC7", "ADC MUX7"},
|
||||
{"IIR0 INP0 MUX", "DEC8", "ADC MUX8"},
|
||||
{"IIR0 INP0 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"IIR0 INP0 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"IIR0", NULL, "IIR0 INP1 MUX"},
|
||||
{"IIR0 INP1 MUX", "DEC0", "ADC MUX0"},
|
||||
{"IIR0 INP1 MUX", "DEC1", "ADC MUX1"},
|
||||
{"IIR0 INP1 MUX", "DEC2", "ADC MUX2"},
|
||||
{"IIR0 INP1 MUX", "DEC3", "ADC MUX3"},
|
||||
{"IIR0 INP1 MUX", "DEC4", "ADC MUX4"},
|
||||
{"IIR0 INP1 MUX", "DEC5", "ADC MUX5"},
|
||||
{"IIR0 INP1 MUX", "DEC6", "ADC MUX6"},
|
||||
{"IIR0 INP1 MUX", "DEC7", "ADC MUX7"},
|
||||
{"IIR0 INP1 MUX", "DEC8", "ADC MUX8"},
|
||||
{"IIR0 INP1 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"IIR0 INP1 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"IIR0", NULL, "IIR0 INP2 MUX"},
|
||||
{"IIR0 INP2 MUX", "DEC0", "ADC MUX0"},
|
||||
{"IIR0 INP2 MUX", "DEC1", "ADC MUX1"},
|
||||
{"IIR0 INP2 MUX", "DEC2", "ADC MUX2"},
|
||||
{"IIR0 INP2 MUX", "DEC3", "ADC MUX3"},
|
||||
{"IIR0 INP2 MUX", "DEC4", "ADC MUX4"},
|
||||
{"IIR0 INP2 MUX", "DEC5", "ADC MUX5"},
|
||||
{"IIR0 INP2 MUX", "DEC6", "ADC MUX6"},
|
||||
{"IIR0 INP2 MUX", "DEC7", "ADC MUX7"},
|
||||
{"IIR0 INP2 MUX", "DEC8", "ADC MUX8"},
|
||||
{"IIR0 INP2 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"IIR0 INP2 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
{"IIR0", NULL, "IIR0 INP3 MUX"},
|
||||
{"IIR0 INP3 MUX", "DEC0", "ADC MUX0"},
|
||||
{"IIR0 INP3 MUX", "DEC1", "ADC MUX1"},
|
||||
{"IIR0 INP3 MUX", "DEC2", "ADC MUX2"},
|
||||
{"IIR0 INP3 MUX", "DEC3", "ADC MUX3"},
|
||||
{"IIR0 INP3 MUX", "DEC4", "ADC MUX4"},
|
||||
{"IIR0 INP3 MUX", "DEC5", "ADC MUX5"},
|
||||
{"IIR0 INP3 MUX", "DEC6", "ADC MUX6"},
|
||||
{"IIR0 INP3 MUX", "DEC7", "ADC MUX7"},
|
||||
{"IIR0 INP3 MUX", "DEC8", "ADC MUX8"},
|
||||
{"IIR0 INP3 MUX", "RX0", "CDC_IF RX0 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX1", "CDC_IF RX1 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX2", "CDC_IF RX2 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX3", "CDC_IF RX3 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX4", "CDC_IF RX4 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX5", "CDC_IF RX5 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX6", "CDC_IF RX6 MUX"},
|
||||
{"IIR0 INP3 MUX", "RX7", "CDC_IF RX7 MUX"},
|
||||
|
||||
{"SRC0", NULL, "IIR0"},
|
||||
{"RX INT0 MIX2 INP", "SRC0", "SRC0"},
|
||||
{"RX INT7 MIX2 INP", "SRC0", "SRC0"},
|
||||
{"RX INT9 MIX2 INP", "SRC0", "SRC0"},
|
||||
|
||||
/* Native clk mix path routing */
|
||||
{"RX INT7_2 NATIVE MUX", "ON", "RX INT7_2 MUX"},
|
||||
{"RX INT7_2 INTERP", NULL, "RX INT7_2 NATIVE MUX"},
|
||||
{"RX INT7_2 NATIVE MUX", NULL, "RX INT7 NATIVE SUPPLY"},
|
||||
|
||||
{"RX INT8_2 NATIVE MUX", "ON", "RX INT8_2 MUX"},
|
||||
{"RX INT8_2 INTERP", NULL, "RX INT8_2 NATIVE MUX"},
|
||||
{"RX INT8_2 NATIVE MUX", NULL, "RX INT8 NATIVE SUPPLY"},
|
||||
|
||||
/* ASRC Routing */
|
||||
{"ASRC2 MUX", "ASRC_IN_SPKR1", "RX INT7_2 INTERP"},
|
||||
{"RX INT7 SEC MIX", NULL, "ASRC2 MUX"},
|
||||
|
||||
{"ASRC3 MUX", "ASRC_IN_SPKR2", "RX INT8_2 INTERP"},
|
||||
{"RX INT8 SEC MIX", NULL, "ASRC3 MUX"},
|
||||
};
|
||||
|
||||
#endif
|
||||
7915
asoc/codecs/wcd9360/wcd9360.c
Normal file
7915
asoc/codecs/wcd9360/wcd9360.c
Normal file
File diff suppressed because it is too large
Load diff
157
asoc/codecs/wcd9360/wcd9360.h
Normal file
157
asoc/codecs/wcd9360/wcd9360.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
* only version 2 as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#ifndef __WCD9360_H__
|
||||
#define __WCD9360_H__
|
||||
|
||||
#include <dsp/apr_audio-v2.h>
|
||||
#include "wcd9360-dsp-cntl.h"
|
||||
#include "../wcd9xxx-slimslave.h"
|
||||
#include "../wcd9xxx-common-v2.h"
|
||||
|
||||
#define WCD9360_REGISTER_START_OFFSET 0x800
|
||||
#define WCD9360_SB_PGD_PORT_RX_BASE 0x40
|
||||
#define WCD9360_SB_PGD_PORT_TX_BASE 0x50
|
||||
#define WCD9360_RX_PORT_START_NUMBER 16
|
||||
|
||||
#define WCD9360_DMIC_CLK_DIV_2 0x0
|
||||
#define WCD9360_DMIC_CLK_DIV_3 0x1
|
||||
#define WCD9360_DMIC_CLK_DIV_4 0x2
|
||||
#define WCD9360_DMIC_CLK_DIV_6 0x3
|
||||
#define WCD9360_DMIC_CLK_DIV_8 0x4
|
||||
#define WCD9360_DMIC_CLK_DIV_16 0x5
|
||||
#define WCD9360_DMIC_CLK_DRIVE_DEFAULT 0x02
|
||||
|
||||
#define WCD9360_ANC_DMIC_X2_FULL_RATE 1
|
||||
#define WCD9360_ANC_DMIC_X2_HALF_RATE 0
|
||||
|
||||
#define PAHU_MAX_MICBIAS 4
|
||||
#define PAHU_NUM_INTERPOLATORS 10
|
||||
#define MAX_ON_DEMAND_SUPPLY_NAME_LENGTH 64
|
||||
|
||||
/* Convert from vout ctl to micbias voltage in mV */
|
||||
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
|
||||
|
||||
|
||||
/* Number of input and output Slimbus port */
|
||||
enum {
|
||||
WCD9360_RX0 = 0,
|
||||
WCD9360_RX1,
|
||||
WCD9360_RX2,
|
||||
WCD9360_RX3,
|
||||
WCD9360_RX4,
|
||||
WCD9360_RX5,
|
||||
WCD9360_RX6,
|
||||
WCD9360_RX7,
|
||||
WCD9360_RX_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
WCD9360_TX0 = 0,
|
||||
WCD9360_TX1,
|
||||
WCD9360_TX2,
|
||||
WCD9360_TX3,
|
||||
WCD9360_TX4,
|
||||
WCD9360_TX5,
|
||||
WCD9360_TX6,
|
||||
WCD9360_TX7,
|
||||
WCD9360_TX8,
|
||||
WCD9360_TX9,
|
||||
WCD9360_TX10,
|
||||
WCD9360_TX11,
|
||||
WCD9360_TX12,
|
||||
WCD9360_TX13,
|
||||
WCD9360_TX14,
|
||||
WCD9360_TX15,
|
||||
WCD9360_TX_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
INTERP_EAR = 0,
|
||||
/* Headset and Lineout are not avalible in pahu */
|
||||
INTERP_HPHL_NA,
|
||||
INTERP_HPHR_NA,
|
||||
INTERP_LO1_NA,
|
||||
INTERP_LO2_NA,
|
||||
INTERP_LO3_NA,
|
||||
INTERP_LO4_NA,
|
||||
INTERP_SPKR1,
|
||||
INTERP_SPKR2,
|
||||
INTERP_AUX,
|
||||
INTERP_MAX,
|
||||
};
|
||||
|
||||
/*
|
||||
* Selects compander and smart boost settings
|
||||
* for a given speaker mode
|
||||
*/
|
||||
enum {
|
||||
WCD9360_SPKR_MODE_DEFAULT,
|
||||
WCD9360_SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
|
||||
};
|
||||
|
||||
/*
|
||||
* Rx path gain offsets
|
||||
*/
|
||||
enum {
|
||||
WCD9360_RX_GAIN_OFFSET_M1P5_DB,
|
||||
WCD9360_RX_GAIN_OFFSET_0_DB,
|
||||
};
|
||||
|
||||
enum {
|
||||
MIC_BIAS_1 = 1,
|
||||
MIC_BIAS_2,
|
||||
MIC_BIAS_3,
|
||||
MIC_BIAS_4
|
||||
};
|
||||
|
||||
enum {
|
||||
MICB_PULLUP_ENABLE,
|
||||
MICB_PULLUP_DISABLE,
|
||||
MICB_ENABLE,
|
||||
MICB_DISABLE,
|
||||
};
|
||||
|
||||
/*
|
||||
* Dai data structure holds the
|
||||
* dai specific info like rate,
|
||||
* channel number etc.
|
||||
*/
|
||||
struct pahu_codec_dai_data {
|
||||
u32 rate;
|
||||
u32 *ch_num;
|
||||
u32 ch_act;
|
||||
u32 ch_tot;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure used to update codec
|
||||
* register defaults after reset
|
||||
*/
|
||||
struct pahu_reg_mask_val {
|
||||
u16 reg;
|
||||
u8 mask;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
extern void *pahu_get_afe_config(struct snd_soc_codec *codec,
|
||||
enum afe_config_type config_type);
|
||||
extern int pahu_cdc_mclk_enable(struct snd_soc_codec *codec, bool enable);
|
||||
extern int pahu_cdc_mclk_tx_enable(struct snd_soc_codec *codec, bool enable);
|
||||
extern int pahu_set_spkr_mode(struct snd_soc_codec *codec, int mode);
|
||||
extern int pahu_set_spkr_gain_offset(struct snd_soc_codec *codec, int offset);
|
||||
extern struct wcd_dsp_cntl *pahu_get_wcd_dsp_cntl(struct device *dev);
|
||||
extern int wcd9360_get_micb_vout_ctl_val(u32 micb_mv);
|
||||
extern int pahu_codec_info_create_codec_entry(
|
||||
struct snd_info_entry *codec_root,
|
||||
struct snd_soc_codec *codec);
|
||||
#endif
|
||||
1158
include/asoc/wcd9360-registers.h
Normal file
1158
include/asoc/wcd9360-registers.h
Normal file
File diff suppressed because it is too large
Load diff
Loading…
Reference in a new issue