From db30227d1795f85a6e77fe9407962386455c9da7 Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Tue, 7 Jul 2020 17:56:09 -0700 Subject: [PATCH] Revert "msm: camera: isp: Disable clk gating in IFE top" This reverts commit 0181a16f13a02f9beaf3cca35b63c33a5a365d82. The control for disabling clock gating is with cpas. So, this change has no effect. CRs-Fixed: 2726688 Change-Id: I74f7d06680d039f8df4e28e8b58d4bd6ad0f650b Signed-off-by: Mukund Madhusudan Atre --- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c index adbd880eabc8..6a66955ed280 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c @@ -366,20 +366,23 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, top_priv->hw_clk_rate = 0; - /* Disable clock gating at IFE top */ - CAM_DBG(CAM_ISP, "Disable clock gating at IFE top"); + /** + * Auto clock gating is enabled by default, but no harm + * in setting the value we expect. + */ + CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top"); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, - common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF); + common_data.common_reg->core_cgc_ovd_0, 0x0); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, - common_data.common_reg->core_cgc_ovd_1, 0xFF); + common_data.common_reg->core_cgc_ovd_1, 0x0); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, - common_data.common_reg->ahb_cgc_ovd, 0x1); + common_data.common_reg->ahb_cgc_ovd, 0x0); cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, - common_data.common_reg->noc_cgc_ovd, 0x1); + common_data.common_reg->noc_cgc_ovd, 0x0); top_priv->top_common.hw_version = cam_io_r_mb(common_data.soc_info->reg_map[0].mem_base +