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ARM: dts: msm: Enable CVP SMMU fault tolerance and Stall disable
"non-fatal" -> smmu will not bug_on for s1 fault. Avoid system crash when CVP SMMU fault happens. CVP SSR can recover SMMU fault now "stall-disable" -> smmu terminates pending transaction Invokes smmu_fault_handler and triggers vnoc interrupt independently. So firmware can quickly write sys_error pkt(previous transactions were not stalled for that CB) to message queue. Change-Id: I749741801dcf2599ccd3b51b53c326629adaebfb
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1 changed files with 3 additions and 0 deletions
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@ -64,6 +64,7 @@
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buffer-types = <0xfff>;
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dma-coherent-hint-cached;
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qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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@ -75,6 +76,7 @@
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buffer-types = <0x741>;
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qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
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qcom,iommu-vmid = <0xB>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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cvp_secure_pixel_cb {
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@ -85,6 +87,7 @@
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buffer-types = <0x106>;
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qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
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qcom,iommu-vmid = <0xA>;
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qcom,iommu-faults = "non-fatal", "stall-disable";
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};
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/* Memory Heaps */
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