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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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MMC core:
- Add some fine-grained hooks to further support HS400 tuning - Improve error path for bus width setting for HS400es - Use a common method when checking R1 status MMC host: - renesas_sdhi: Add r8a77990 support - renesas_sdhi: Add eMMC HS400 mode support - tmio/renesas_sdhi: Improve tuning/clock management - tmio: Add eMMC HS400 mode support - sunxi: Add support for 3.3V eMMC DDR mode - mmci: Initial support to manage variant specific callbacks - sdhci: Don't try 3.3V I/O voltage if not supported - sdhci-pci-dwc-mshc: Add driver to support Synopsys dwc mshc SDHCI PCI - sdhci-of-dwcmshc: Add driver to support Synopsys DWC MSHC SDHCI - sdhci-msm: Add support for new version sdcc V5 - sdhci-pci-o2micro: Add support for O2 eMMC HS200 mode - sdhci-pci-o2micro: Add support for O2 hardware tuning - sdhci-pci-o2micro: Add MSI interrupt support for O2 SD host - sdhci-pci: Add support for Intel ICP - sdhci-tegra: Prevent ACMD23 and HS200 mode on Tegra 3 - sdhci-tegra: Fix eMMC DDR52 mode - sdhci-tegra: Improve clock management - dw_mmc-rockchip: Document compatible string for px30 - sdhci-esdhc-imx: Add support for 3.3V eMMC DDR mode - sdhci-of-esdhc: Set proper DMA mask for ls104x chips - sdhci-of-esdhc: Improve clock management - sdhci-of-arasan: Add a quirk to manage unstable clocks - dw_mmc-exynos: Address potential external abort during system resume - pxamci: Add support for common MMC DT bindings - pxamci: Several cleanups and improvements - pxamci: Merge immutable branch for pxa to switch to DMA slave maps -----BEGIN PGP SIGNATURE----- iQJLBAABCgA1FiEEugLDXPmKSktSkQsV/iaEJXNYjCkFAlt2n1YXHHVsZi5oYW5z c29uQGxpbmFyby5vcmcACgkQ/iaEJXNYjCmEEQ//eBA9mdUWF4Jdq/taazJfDeRQ /a9EJNRivr6xeOh4wq48v50/FtKD48r8112DXmyKfXhbhc4mgo5z03b6YwOGE+JE A3gQgNx4cZE0IMis9TGikHU52nSljsdPeCyiQ84tS8Lh9zgj/lRsHnkd8GKTh6FR eBeZmtS9RyionI98NhNQecjPlIrvm+dw0X+OTRLQewKefstNL8Ut1zyC6BPBXaHh MDEfo2nQ0yirATl1SSUlLRb4vmSGYbgqsiwoqC3zMLwqt7awIRqqEupRzqDGjW1d RniN6GzJEzfQqJ4AfY/IpE8EUzqM8BKBYKoEYgv67XTJAceA7Z3mQSec1pC8IHQ9 8PLOEm17MeuQSNXVjbRXkMqA2z9+bewexVxpkRmZHorlzLNw0violJs7tvi09gYk g6zlAXVocLlbXep3LQFCo333M7Qhzp1dHzpIdcS151kPkAJnyyNSN5m2/Dvsi426 OgFa/D8fCr6XJLFVYhU+RXIbCSoQx7l5i5iUsrbgKbtbjXr28YoVFn/IbJojqBeu vZY8+LDvAJNrVuRYPAmvEsDhjeheOaAYKLYBBjxnSOpYwgcCLQ1wJ3jVpKooYhgm bH1q+8qDz30dr3mZjR1QqpxWrmdfMer8N5DxpDwCQU5JhctdEMoiJM15G5hwO5VZ WknaOY46inLBZrEmurs= =5jpq -----END PGP SIGNATURE----- Merge tag 'mmc-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc Pull MMC updates from Ulf Hansson: "Updates for MMC for v4.19. MMC core: - Add some fine-grained hooks to further support HS400 tuning - Improve error path for bus width setting for HS400es - Use a common method when checking R1 status MMC host: - renesas_sdhi: Add r8a77990 support - renesas_sdhi: Add eMMC HS400 mode support - tmio/renesas_sdhi: Improve tuning/clock management - tmio: Add eMMC HS400 mode support - sunxi: Add support for 3.3V eMMC DDR mode - mmci: Initial support to manage variant specific callbacks - sdhci: Don't try 3.3V I/O voltage if not supported - sdhci-pci-dwc-mshc: Add driver to support Synopsys dwc mshc SDHCI PCI - sdhci-of-dwcmshc: Add driver to support Synopsys DWC MSHC SDHCI - sdhci-msm: Add support for new version sdcc V5 - sdhci-pci-o2micro: Add support for O2 eMMC HS200 mode - sdhci-pci-o2micro: Add support for O2 hardware tuning - sdhci-pci-o2micro: Add MSI interrupt support for O2 SD host - sdhci-pci: Add support for Intel ICP - sdhci-tegra: Prevent ACMD23 and HS200 mode on Tegra 3 - sdhci-tegra: Fix eMMC DDR52 mode - sdhci-tegra: Improve clock management - dw_mmc-rockchip: Document compatible string for px30 - sdhci-esdhc-imx: Add support for 3.3V eMMC DDR mode - sdhci-of-esdhc: Set proper DMA mask for ls104x chips - sdhci-of-esdhc: Improve clock management - sdhci-of-arasan: Add a quirk to manage unstable clocks - dw_mmc-exynos: Address potential external abort during system resume - pxamci: Add support for common MMC DT bindings - pxamci: Several cleanups and improvements - pxamci: Merge immutable branch for pxa to switch to DMA slave maps" * tag 'mmc-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (56 commits) mmc: core: improve reasonableness of bus width setting for HS400es mmc: tmio: remove unneeded variable in tmio_mmc_start_command() mmc: renesas_sdhi: Fix sampling clock position selecting mmc: tmio: Fix tuning flow mmc: sunxi: remove output of virtual base address dt-bindings: mmc: rockchip-dw-mshc: add description for px30 mmc: renesas_sdhi: Add r8a77990 support mmc: sunxi: allow 3.3V DDR when DDR is available mmc: mmci: Add and implement a ->dma_setup() callback for qcom dml mmc: mmci: Initial support to manage variant specific callbacks mmc: tegra: Force correct divider calculation on DDR50/52 mmc: sdhci: Add MSI interrupt support for O2 SD host mmc: sdhci: Add support for O2 hardware tuning mmc: sdhci: Export sdhci tuning function symbol mmc: sdhci: Change O2 Host HS200 mode clock frequency to 200MHz mmc: sdhci: Add support for O2 eMMC HS200 mode mmc: tegra: Add and use tegra_sdhci_get_max_clock() mmc: sdhci-esdhc-imx: fix indent mmc: sdhci-esdhc-imx: disable clocks before changing frequency mmc: tegra: prevent ACMD23 on Tegra 3 ...
This commit is contained in:
commit
bbd60bffaf
43 changed files with 1373 additions and 494 deletions
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@ -37,6 +37,8 @@ Optional Properties:
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- xlnx,fails-without-test-cd: when present, the controller doesn't work when
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the CD line is not connected properly, and the line is not connected
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properly. Test mode can be used to force the controller to function.
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- xlnx,int-clock-stable-broken: when present, the controller always reports
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that the internal clock is stable even when it is not.
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Example:
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sdhci@e0100000 {
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@ -8,10 +8,9 @@ Required properties:
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Optional properties:
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- marvell,detect-delay-ms: sets the detection delay timeout in ms.
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- marvell,gpio-power: GPIO spec for the card power enable pin
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This file documents differences between the core properties in mmc.txt
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and the properties used by the pxa-mmc driver.
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In addition to the properties described in this docuent, the details
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described in mmc.txt are supported.
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Examples:
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@ -19,6 +18,7 @@ mmc0: mmc@41100000 {
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compatible = "marvell,pxa-mmc";
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reg = <0x41100000 0x1000>;
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interrupts = <23>;
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vmmc-supply = <&mmc_regulator>;
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cd-gpios = <&gpio 23 0>;
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wp-gpios = <&gpio 24 0>;
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};
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@ -14,6 +14,7 @@ Required Properties:
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before RK3288
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- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
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- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
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- "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip PX30
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- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
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- "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK322x
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- "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3328
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@ -4,7 +4,12 @@ This file documents differences between the core properties in mmc.txt
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and the properties used by the sdhci-msm driver.
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Required properties:
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- compatible: Should contain "qcom,sdhci-msm-v4".
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- compatible: Should contain:
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"qcom,sdhci-msm-v4" for sdcc versions less than 5.0
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"qcom,sdhci-msm-v5" for sdcc versions >= 5.0
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For SDCC version 5.0.0, MCI registers are removed from SDCC
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interface and some registers are moved to HC. New compatible
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string is added to support this change - "qcom,sdhci-msm-v5".
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- reg: Base address and length of the register in the following order:
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- Host controller register map (required)
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- SD Core register map (required)
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20
Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
Normal file
20
Documentation/devicetree/bindings/mmc/sdhci-of-dwcmshc.txt
Normal file
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@ -0,0 +1,20 @@
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* Synopsys DesignWare Cores Mobile Storage Host Controller
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Required properties:
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- compatible: should be one of the following:
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"snps,dwcmshc-sdhci"
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- reg: offset and length of the register set for the device.
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- interrupts: a single interrupt specifier.
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- clocks: Array of clocks required for SDHCI; requires at least one for
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core clock.
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- clock-names: Array of names corresponding to clocks property; shall be
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"core" for core clock and "bus" for optional bus clock.
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Example:
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sdhci2: sdhci@aa0000 {
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compatible = "snps,dwcmshc-sdhci";
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reg = <0xaa0000 0x1000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&emmcclk>;
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bus-width = <8>;
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}
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@ -28,6 +28,7 @@ Required properties:
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"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
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"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
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"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
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"renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
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"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
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"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
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"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
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